GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 813754
Date 1/24/2025
Public

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7.2.2. PCI Express* Capability Structures

The layouts of the most basic capability structures are provided below. Refer to the PCI Express* Base Specification for more information about these registers.

Figure 63. Power Management Capability Structure—Byte Address Offsets and Layout
Figure 64. MSI Capability Structure
Figure 65.  PCI Express* Capability Structure—Byte Address Offsets and Layout
Figure 66. MSI-X Capability Structure
Figure 67.  PCI Express* AER Extended Capability Structure

Refer to the Excel-based GTS AXI Streaming Intel FPGA IP for PCI Express* Register Map for the detailed descriptions of the registers.