Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
ID
813663
Date
9/01/2025
Public
1. Low Latency Ethernet 10G MAC IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC IP Core
5. Interface Signals
6. Configuration Registers
7. Debug Checklist
8. Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs Archives
9. Document Revision History for the Low Latency Ethernet 10G MAC IP User Guide: Agilex™ 3 and Agilex™ 5 FPGAs and SoCs
2.1. Introduction to Altera IP Cores
2.2. Installing and Licensing IP Cores
2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
2.4. Generated File Structure
2.5. Simulating IP Cores
2.6. Upgrading the Low Latency Ethernet 10G MAC IP Core
2.7. Low Latency Ethernet 10G MAC IP Design Examples
5.1. Clock and Reset Signals
5.2. Speed Selection Signal
5.3. Error Correction Signals
5.4. Unidirectional Signals
5.5. Avalon® Memory-Mapped Interface Programming Signals
5.6. Avalon® Streaming Data Interfaces
5.7. Avalon® Streaming Flow Control Signals
5.8. Avalon® Streaming Status Interface
5.9. PHY-side Interfaces
5.10. IEEE 1588v2 Interfaces
6.1. Register Map
6.2. Register Access Definition
6.3. Primary MAC Address
6.4. MAC Reset Control Register
6.5. TX Configuration and Status Registers
6.6. Flow Control Registers
6.7. Unidirectional Control Registers
6.8. RX Configuration and Status Registers
6.9. ECC Registers
6.10. Statistics Registers
6.11. Timestamp Registers
6.3. Primary MAC Address
Word Offset | Register Name | Description | Access | HW Reset Value |
---|---|---|---|---|
0x0010 | primary_mac_addr0 | 6-byte primary MAC address. Configure this register with a non-zero value before you enable the MAC IP core for operations. Map the primary MAC address as follows:
If the primary MAC address is 00-1C-23-17-4A-CB, set primary_mac_addr0 to 0x23174ACB and primary_mac_addr1 to 0x0000001C. UsageOn transmit, the MAC IP core uses this address to fill the source address field in control frames. For data frames from the client, the MAC IP core replaces the source address field with the primary MAC address when the tx_src_addr_override register is set to 1. On receive, the MAC IP core uses this address to filter unicast frames when the EN_ALLUCAST bit of the rx_frame_control register is set to 0. The MAC IP core drops frames whose destination address is different from the value of the primary MAC address. |
RW | 0x0 |
0x0011 | primary_mac_addr1 |