Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 8/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Compiling and Simulating the Design Example 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.4. Compiling and Simulating the Design Example x
1.4.1. Simulation Design Example Components
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

2.4.2. Packet Client Registers

Table 6.  Types of Register Access
Access Definition
RO Read only.
RW Read and write.
RWC Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP clears the bit(s) upon executing the instruction.
Table 7.  Packet Client Registers You can customize the Low Latency 40G Ethernet Intel® FPGA IP hardware design example for Agilex™ 5 devices by programming the packet client registers.
Address Name Bit Description

HW Reset Value

Access

0x1000 PKT_CL_SCRATCH [31:0] Scratch register available for testing. — RW
0x1001 PKT_CL_CLNT [31:0] Four characters of IP block identification string "CLNT". — RO
0x1003 rx_status [31:0]
  • Bit [0]: rx_pcs_ready
  • Bit [1]: rx_am_lock
  • Bit [2]: rx_block_lock
— RO
0x1004 tx_pkt_cnt [31:0] Total number of packets transferred in the transmit direction. — RO
0x1005 rx_pkt_cnt [31:0] Total number of packets transferred in receive direction. — RO
0x1006 rx_err_cnt [31:0] Total number of packets received with error. — RO
0x1007 control [31:0]
  • Bit [0]: Used to reset both transmit and receive counters, Active high reset.
  • Bit [1]: Used to reset the counter for dropped blocks, Active high reset.
 — RW
0x1008 Packet Size Configure [29:0] Specify the transmit packet size in bytes. These bits have dependencies to PKT_GEN_TX_CTRL register.
  • Bit [29:16]: Specify the upper limit of the packet size in bytes. This is only applicable to incremental mode.
  • Bit [13:0]:
    • For fixed mode, these bits specify the transmit packet size in bytes.
    • For incremental mode, these bits specify the lower limit of the transmit packet size in bytes.
 0x25800040 RW
0x1009 Packet Number Control [31:0] Specify the number of packets to transmit from the packet generator. 0xA RW
0x1010 PKT_GEN_TX_CTRL [7:0]
  • Bit [0]: Reserved.
  • Bit [1]: Packet generator status control bit.
    • 0: Turn off the packet generator.
    • 1: Turn on the packet generator.
  • Bit [2]: Reserved.
  • Bit [3]: Has the value of 1 if the IP is in MAC loopback mode; has the value of 0 if the packet client uses the packet generator.
  • Bit [5:4]:
    • 00: Random mode
    • 01: Fixed mode
    • 10: Incremental mode
  • Bit [6]: Set this bit to 1 to use 0x1009 register to turn off packet generator based on a fixed number of packets to transmit. Otherwise, use bit [1] of the PKT_GEN_TX_CTRL register to turn off the packet generator.
  • Bit [7]:
    • 1: For transmission without gap in between packets.
    • 0: For transmission with random gap in between packets.
 0x6 RW
0x1011 Destination address lower 32 bits [31:0] Destination address (lower 32 bits) 0x56780ADD RW
0x1012 Destination address upper 16 bits [15:0] Destination address (upper 16 bits) 0x1234 RW
0x1013 Source address lower 32 bits [31:0] Source address (lower 32 bits) 0x43210ADD RW
0x1014 Source address upper 16 bits [15:0] Source address (upper 16 bits) 0x8765 RW
Level Two Title