Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 8/16/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Compiling and Simulating the Design Example 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.4. Compiling and Simulating the Design Example x
1.4.1. Simulation Design Example Components
2. Design Example Description x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

2.4.1. Hardware Design Example Register Map

Table 5.   Low Latency 40G Ethernet Hardware Design Example Register MapLists the memory mapped register ranges for the hardware design example. You access these registers with the reg_read and reg_write functions in the System Console. For more information about these registers (except packet client registers), refer to the Low Latency 40G Ethernet Intel® FPGA IP User Guide: Intel Agilex® 5 FPGAs and SoCs .
Byte Address Block
0x300 – 0x3FF PHY registers
0x400 – 0x4FF TX MAC registers
0x500 – 0x5FF RX MAC registers
0x600 – 0x7FF Flow control registers
0x800 – 0x8FF TX statistics counters
0x900 – 0x9FF RX statistics counters
0x1000 – 0x1014 Packet client registers
Level Two Title