Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Compiling and Simulating the Design Example 1.5. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.4. Compiling and Simulating the Design Example x
1.4.1. Simulation Design Example Components
2. Design Example Description x
2.1. Features 2.2. Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

1.4.1. Simulation Design Example Components

The simulation design example top-level test file is basic_avl_tb_top.sv. This file provides a clock reference clk_ref_p of 156.25 MHz to the PHY. It includes a task to send and receive 10 packets.

Table 3.  Testbench File Descriptions

File Names

Description

Key Testbench and Simulation Files

basic_avl_tb_top.v Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.

Testbench Scripts

run_vsim.do

The Siemens* EDA QuestaSim* script to run the testbench.

run_vcs.sh

The Synopsys* VCS* script to run the testbench.

run_vcsmx.sh

The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench.

run_xcelium.sh The Cadence* Xcelium* script to run the testbench.
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