Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813654
Date 4/01/2024
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Command Line IP Generation Flow 1.4. Compiling and Simulating the Design Example 1.5. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
1.4. Compiling and Simulating the Design Example x
1.4.1. Simulation Design Example Components
2. Design Example Description x
2.1. Features 2.2. Software Requirements 2.3. Functional Description 2.4. Design Example Registers 2.5. Design Example Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Design Example Registers x
2.4.1. Hardware Design Example Register Map 2.4.2. Packet Client Registers
1. Quick Start Guide
2. Design Example Description
3. Document Revision History for the Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide

1.3. Command Line IP Generation Flow

  1. Run the following command: 
    qsys-edit --new-component-type=intel_eth_e40 --family=Agilex5 --
part=<part_name> --new-quartus-project=<project_name>
    For example: 
    qsys-edit --new-component-type=intel_eth_e40 --family=Agilex5 --part=A5ED065BB32AE5SR0 intel_eth_e40.ip
  2. In the pop-up GUI, select the New Quartus Project option to create a new project (.qpf) with intel_eth_e40.ip included.
  3. Select Create.
Figure 4. Low Latency 40G Ethernet Intel FPGA IP GUI After Command Line Instructions
Level Two Title