7.1. PHY Registers
Addr | Name | Description | Reset | Access |
---|---|---|---|---|
0x00 | REVID | IP PHY module revision ID. | 0x0627 2016 | RO |
0x01 | SCRATCH | Scratch register available for testing. | 0x0000 0000 | RW |
0x02 | PHY_NAME_0 | First characters of IP variation identifier string. | 0x0000 3430 | RO |
0x03 | PHY_NAME_1 | Next characters of IP variation identifier string. | 0x0000 4745 | RO |
0x04 | PHY_NAME_2 | Final characters of IP variation identifier string. | 0x0070 6373 | RO |
0x10 | PHY_CONFIG | PHY configuration registers. The following bit fields are defined:
|
0bxxxx xxxx xxxx xxxx xxxx xxxx xx00 x000 | RW |
0x12 | WORD_LOCK | When asserted, indicates that the virtual channel has identified 66-bit block boundaries in the serial data stream. | 0xXXXX XXX0 | RO |
0x14 | EIO_FLAG_SEL | Supports indirect addressing of individual FIFO flags in the PCS Direct PHY IP. This is a binary encoded value and the flags are set as below for bits [20:0]:
|
0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx x000 | RW |
0x15 | EIO_FLAGS | PCS indirect data. To read a FIFO flag, set the corresponding bit in the PHY_PCS_INDIRECT_ADDR register. After you specify the flag in the PHY_PCS_INDIRECT_ADDR register, each bit [n] in the PHY_PCS_INDIRECT_ADDR register has the value of the corresponding transceiver FIFO flag. | 0xXXXX XXX0 | RO |
0x21 | EIO_FREQ_LOCK | Each asserted bit indicates that the corresponding lane RX clock data recovery (CDR) phase-locked loop (PLL) is locked. | 0xXXXX XXX0 | RO |
0x22 | PHY_CLK | The following encodings are defined:
|
0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx x000 | RO |
0x23 | FRM_ERR | Each asserted bit indicates that the corresponding virtual lane has a frame error. These bits are sticky. You clear them with the PHY_SCLR_FRAME_ERROR register. If the IP loses word lock, it clears this register. |
0xXXXX XXX0 | RO |
0x24 | SCLR_FRM_ERR | Synchronous clear for PHY_FRAME_ERROR register. Write a value of 1 to this register to clear the PHY_FRAME_ERROR register. Then need to write 0 to this register to let PCS RX working properly. Keep this register as 1 causes PCS link lost. | 0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0 | RW |
0x25 | EIO_RX_SOFT_PURGE_S | Set bit [0] to clear the RX FIFO for all four physical lanes.
|
0bx0 0xxx xxxx xxx0 | RO |
0x26 | RX_PCS_FULLY_ALIGNED_S | Indicates the RX PCS is fully aligned and ready to accept traffic.
|
0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0 | RO |
0x28 | AM_LOCK | When asserted, indicates that the physical channel has identified virtual lane alignment markers in the data stream. This is a one-bit signal. | 0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxx0 | |
0x29 | LANE_DESKEWED |
The following encodings are defined:
After reset, the lane_deskewed value is undefined before RX clock is up |
0bxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx | RO |
0x30 | PCS_VLANE | The following encodings are defined:
|
0xXXXX XX00 | RO |
0x31 | PHY_RX_DELAY | Test and debug feature to test deskew. Allows you to insert a programmable skew on one physical channel. It is a 6 bit register with these fields:
Note: Due to the FIFO based implementation of word-delay logic, the minimum value for word-delay (Bits 1-5) is 2 corresponding to a delay of one cycle. This ensures that the FIFOs read/write pointers are collision free.
|
0bxxxx xxxx xxxx xxxx xxxx xxxx xx00 0000 | RW |
0x41 | KHZ_RX | The register indicates the value of RX clock (clk_rxmac) frequency. Apply the following definition for the frequency value: [(Register value 2 * clk_status)/10] KHz |
0x0000 0000 | RO |
0x42 | KHZ_TX | The register indicates the value of TX clock (clk_txmac) frequency. Apply the following definition for the frequency value: [(Register value 2 * clk_status)/10] KHz |
0x0000 0000 | RO |
1 X means "Don't Care".
2 Register value convert in decimal.