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1. About the Low Latency 40G Ethernet Intel® FPGA IP
2. Low Latency 40G Ethernet Intel® FPGA IP Parameters
3. Getting Started
4. Functional Description
5. Clocking and Reset Requirements
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Comparison Between Various Low Latency 40G Ethernet Intel® FPGA IPs
9. Document Revision History for Low Latency 40G Ethernet Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
6.1. TX MAC Interface to User Logic
6.2. RX MAC Interface to User Logic
6.3. GTS Transceivers Signals
6.4. GTS Transceiver Reconfiguration Signals
6.5. Avalon® Memory-Mapped Management Interface
6.6. Miscellaneous Status and Debug Signals
6.7. Reset Signals
6.8. Clocks
6.9. Flow Control Interface
6.10. GTS Reset Sequencer Intel® FPGA IP
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4.3.5. TX Avalon® Streaming Filter
The TX Avalon® streaming filter is added in TX adapter to monitor incoming Avalon® streaming TX traffic. When an illegal packet occurs, it raises an error signal. To prevent incorrect behavior downstream, the TX Avalon® streaming filter removes some illegal packets. When illegal patterns occur, it raises the error flag, so that you can be aware of the problem. Some of the illegal traffic patterns are also filtered to prevent downstream problems.