AXI Streaming Intel® FPGA IP for PCI Express* User Guide

ID 790711
Date 1/24/2025
Public
Document Table of Contents

3.6.1.1.2. VCS* Simulator

To run simulations using the VCS* simulator, follow these steps:

  1. Go to the working directory: cd <my_design>/pcie_ss_ed_sim_tb/pcie_ss_ed_sim_tb/sim/synopsys/vcs/
  2. Type: sh run_vcs.sh
  3. A successful simulation ends with the following message, "Simulation stopped due to successful completion!".
    Note:
    To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in non-interactive mode, delete the simv and simv.diadir)
    1. Open the vcs_setup.sh file and add a debug option to the VCS command: vcs -debug_access+all.
    2. Compile the design example: sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="+define+rnrb_one_lib_RNR_OVERCLK_FASTSIM\ +define+RTILE_PIPE_MODE\ +define+RNR_FASTSIM_AIB_BYPASS\ +define+rnrb_one_lib_RNR_PCIE_TOP_EQ_BYPASS_FASTSIM\ +define+rnrb_one_lib_RNR_PCIE_TOP_EQ_BYPASS_FASTSIM_H2H\ +define+rnrb_one_lib_RNR_FASTSIM_FORCE_PLL_LOCK_TIME\ +define+XTOR_PCIECXL_LM_SVS_SERDES_ARCHITECTURE\ +define+rnrc_one_lib_RNR_OVERCLK_FASTSIM\ +define+rnrc_one_lib_RNR_PCIE_TOP_EQ_BYPASS_FASTSIM\ +define+rnrc_one_lib_RNR_PCIE_TOP_EQ_BYPASS_FASTSIM_H2H\ +define+rnrc_one_lib_RNR_FASTSIM_FORCE_PLL_LOCK_TIME\ +define+XTOR_PCIECXL_LM_SVS_SERDES_ARCHITECTURE" USER_DEFINED_SIM_OPTIONS="" TOP_LEVEL_NAME="pcie_ss_ed_sim_tb" SKIP_SIM=1 | tee simulation.log.
    3. Start the simulation in interactive mode: simv -gui &.
    Note: For details on the testbench, refer to Simulating the Design Example.