AN 1003: Multi Memory IP System Resource Planning: for Agilex™ 7 M-Series FPGAs

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ID 788295
Date 2/07/2025
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. About This Application Note 2. Component Bandwidth Projections and Limitations 3. Resource Planning for Agilex™ 7 M-Series FPGAs 4. Factors Affecting NoC Performance 5. Debugging the NoC 6. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Agilex™ 7 M-Series FPGAs
1. About This Application Note x
1.1. Preliminary Guidelines 1.2. Document Prerequisites 1.3. Terminology for Agilex™ 7 M-Series FPGAs
2. Component Bandwidth Projections and Limitations x
2.1. Memory Controller Efficiency 2.2. Hard Memory NoC Bandwidth 2.3. Overall Bandwidth for NoC Systems
2.1. Memory Controller Efficiency x
2.1.1. HBM2E UIB Controller Efficiency 2.1.2. External Memory Interface Controller Efficiency
2.2. Hard Memory NoC Bandwidth x
2.2.1. Horizontal NoC Bandwidth 2.2.2. Initiator NoC Bandwidth 2.2.3. Target NoC Bandwidth 2.2.4. Initiator Target Link Bandwidth
3. Resource Planning for Agilex™ 7 M-Series FPGAs x
3.1. Hard Memory NoC Resource Planning Overview 3.2. I/O Bank Blockage 3.3. Planning Avalon® Streaming Utilization 3.4. Planning for Initiator Blockage Impact from GPIO, LVDS SERDES, and PHY Lite Bypass Mode 3.5. Planning NoC PLL and I/O PLL 3.6. Pin Planning for HPS EMIF 3.7. Planning for an External Memory Interface 3.8. Planning for HBM2E 3.9. Planning for the Fabric NoC 3.10. Planning for AXI4-Lite 3.11. Planning NoC and Memory Solution Clocks
3.2. I/O Bank Blockage x
3.2.1. Top Hard Memory NoC 3.2.2. Bottom Hard Memory NoC
3.10. Planning for AXI4-Lite x
3.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC 3.10.2. AXI4-Lite Initiator for HBM2E 3.10.3. AXI4-Lite Initiator for EMIF
3.11. Planning NoC and Memory Solution Clocks x
3.11.1. Clocking without the Fabric NoC 3.11.2. Clocking with the Fabric NoC
4. Factors Affecting NoC Performance x
4.1. Recommended Performance Tuning Procedure 4.2. NoC Initiator and Target Clock Rate 4.3. Recommended NoC Design Topologies 4.4. Traffic Access Pattern and Memory Controller Efficiency 4.5. Traffic Access Pattern Due To Multiple Traffic Flows 4.6. Transaction Size 4.7. Congestion Interaction 4.8. Bandwidth Sharing At Each Switch 4.9. Exceeding NoC Bandwidth Limits 4.10. Maximum Number of Outstanding Transactions 4.11. QoS Priority 4.12. AxID 4.13. Example: 2x2 HBM Crossbars 4.14. Example: 16x16 Crossbar
4.3. Recommended NoC Design Topologies x
4.3.1. 1:1 Connectivity with EMIF and HBM 4.3.2. HBM Crossbars 4.3.3. Connectivity with HPS
5. Debugging the NoC x
5.1. Debugging NoC AXI Transaction Issues 5.2. Debugging NoC Bit Errors 5.3. Debugging NoC Performance Issues
5.3. Debugging NoC Performance Issues x
5.3.1. Measuring Performance with the Signal Tap Logic Analyzer 5.3.2. Measuring Performance with the Performance Monitor 5.3.3. Performance Debug Steps
Answers to Top FAQs
1. About This Application Note
2. Component Bandwidth Projections and Limitations
3. Resource Planning for Agilex™ 7 M-Series FPGAs
4. Factors Affecting NoC Performance
5. Debugging the NoC
6. Document Revision History of AN 1003: Multi Memory IP System Resource Planning for Agilex™ 7 M-Series FPGAs

3.10.1. Single AXI4 Lite Initiator for Each Horizontal NoC

If your application requires many sideband operations through the AXI4-Lite interface, and if you can afford a separate initiator only for sideband operations, place this initiator close to the NoC SSM. This placement reduces latency and congestion on the mainband network.

When you select a single initiator for the sideband of all memories (EMIFs and HBM2E) on the same side of the hard memory NoC, this arrangement reduces the congestion on the initiator and mainband network.

You can also choose to use an independent initiator for AXI4-Lite for each type of memory, one for EMIF and one for HBM2E, on the same side of the hard memory NoC. Depending on memory requirement of your application, you may need one or two initiators for AXI4-Lite sideband operations. While this arrangement requires more initiators, it offers more flexibility and potentially better performance for sideband operations.

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