AN 1003: Multi Memory IP System Resource Planning: for Agilex™ 7 M-Series FPGAs

ID 788295
Date 2/07/2025
Public
Document Table of Contents

5. Debugging the NoC

This chapter provides various strategies for debugging different problems that you can encounter with the NoC in Agilex™ 7 M-Series FPGAs.

It is most effective to implement these debug strategies in order because later debugging strategies in this chapter build on the improvements of earlier strategies of the chapter.

Note: For debugging issues specific to the External Memory Interfaces Intel Agilex 7 M-Series FPGA IP or the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP, such as calibration failures, refer to the corresponding IP user guides.