Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide

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ID 782461
Date 7/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Quartus® Prime Software and Driver Installation
2.3. Quartus® Prime Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.3. Installing the Development Kit 2.3.4. Installing the Altera® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control the On-board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Information Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMC+ NRZ Tab 4.2.5.4. The QSFPDD800 PAM4 Tab
4.2.6. The Memory Tab x
4.2.6.1. The DDR5 COMP Tab 4.2.6.2. The LP DDR5 COMP Tab 4.2.6.3. The HPS DDR5 COMP Tab 4.2.6.4. The DDR5 RDIMM Tab 4.2.6.5. The HBM2 Tab
4.2.6.5. The HBM2 Tab x
4.2.6.5.1. The HBM2 Top Tab 4.2.6.5.2. The HBM2 Bottom Tab
4.3. Control the On-board Clock through Clock Controller GUI x
4.3.1. Si5391-1 4.3.2. Si5391-2 4.3.3. Si5392 4.3.4. Si5395 4.3.5. Si5332 4.3.6. Si5518
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device Using the Avalon® Streaming Interface x8 Configuration Mode 5.3. Daughter Card
5.3. Daughter Card x
5.3.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Power A.2. Clocks A.3. General Input/Output A.4. Memory Interfaces A.5. Communication Interfaces A.6. Daughter Card A.7. Connectors and Cables
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide

Document Version Changes
2025.07.30
  • Updated Overview.
  • Updated the notes for the S16 and S20 switches in Table: Factory Default Switch Settings.
  • Updated Performing Board Restore.
  • Updated Restoring Board QSPI Flash with Default Factory Image.
  • Updated the steps in Configuring FPGA Device Using the Avalon® Streaming Interface x8 Configuration Mode.
  • Updated the Development Kit Components appendix chapter:
    • Updated information about 2x MCIO x8 connector in Communication Interfaces.
    • Updated the table in Connectors and Cables
      • Updated the MCIO cable part number from "HMC74-0631" to "HMC74-1492".
      • Removed Notes column.
2025.04.07
  • Updated the device part number for DK-DEV-AGM039EA in Table: Ordering Information.
  • Updated the Getting Started chapter:
    • Added new topic—Installing the Ashling* RiscFree* Integrated Development Environment (IDE).
    • Removed Installing the Intel® SoC EDS.
    • Updated demos and examples directory descriptions in Table: Installed Development Kit Directory Description.
  • Updated Table: Factory Default Switch Settings in the Development Kit Setup chapter.
  • Updated the Board Test System chapter:
    • Updated Setting Up the Quartus® Prime Software for BTS Operation.
    • Updated step 2 in Running the BTS GUI.
    • Updated all figures.
    • Removed the QSFPDD PRESENT STATUS control information in The GPIO Tab.
    • Updated and retitled topic Transceiver Designs to The XCVR Tab.
    • Updated the Detail description in The QSFPDD NRZ Tab.
    • Added new section—The Memory Tab.
    • Updated the Import description in Si5518.
    • Updated Monitor On-Board Power Regulator through Power Monitor GUI:
      • Updated the Local Temp description.
      • Added a note for the Temperature Range for Fan Control.
  • Updated Configuring FPGA and Accessing HPS Debug Access Port by JTAG in the Development Kit Hardware and Configuration chapter.
  • Updated Table: Agilex™ 7 FPGA M-Series HBM2e Development Kit References in the Developer Resources chapter.
  • Updated the description for FPGA and HPS shared external memory interface (LPDDR5 component) in the Memory Interfaces appendix chapter.
  • Made editorial edits throughout the document.
  • Updated the document for the latest branding standards.
2024.12.04
  • Updated the Overview chapter:
    • Updated Table: Ordering Information.
    • Retitled figure Agilex™ 7 FPGA M-Series HBM2e Development Kit Top to Agilex™ 7 FPGA M-Series HBM2e Development Kit—Top View.
  • Updated the Getting Started chapter:
    • Added new topics:
      • Before You Begin
      • Handling the Board
      • Installing the Quartus® Prime Pro Edition Software
      • Installing the Intel® SoC EDS
      • Installing the Development Kit
      • Installing the Altera® FPGA Download Cable II Driver
    • Updated Quartus® Prime Software and Driver Installation.
    • Removed Design Examples.
  • Updated the Board Test System chapter:
    • Updated the following topics:
      • Downloading OpenJDK
      • Installing OpenJDK and OpenJFX
      • Transceiver Designs
      • Control the On-board Clock through Clock Controller GUI
      • Monitor On-Board Power Regulator through Power Monitor GUI
    • Retitled topic Installing the Quartus® Prime Software to Setting Up the Quartus® Prime Software for BTS Operation.
  • Updated information about MCIO port in the Appendix A.5—Communication Interfaces.
  • Added new appendix chapter—Developer Resources.
  • Retitled appendix chapter Additional Information to Safety and Regulatory Compliance Information.
  • Restructured the document to improve clarity and for ease of reference.
  • Updated the document for the latest branding standards.
2024.05.14
  • Retitled the document from Intel Agilex® 7 M-Series HBM2e Development Kit User Guide to Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide.
  • Removed mention of Agilex™ 9 from the document.
  • Removed information related to 256 MB QSPI flash daughter card in Appendix: Daughter Cards.
  • Updated document per latest branding standards.
2024.01.24 Updated Figure: Intel Agilex® 7 FPGA M-Series HBM2e Development Kit Block Diagram.
2023.11.03 Initial release.
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