Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide

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ID 782461
Date 7/30/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Board Test System 5. Development Kit Hardware and Configuration 6. Custom Projects for the Development Kit 7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide A. Development Kit Components B. Developer Resources C. Safety and Regulatory Compliance Information
1. Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Box Contents 1.4. Recommended Operating Conditions
2. Getting Started x
2.1. Before You Begin 2.2. Handling the Board 2.3. Quartus® Prime Software and Driver Installation
2.3. Quartus® Prime Software and Driver Installation x
2.3.1. Installing the Quartus® Prime Pro Edition Software 2.3.2. Installing the Ashling* RiscFree* Integrated Development Environment (IDE) 2.3.3. Installing the Development Kit 2.3.4. Installing the Altera® FPGA Download Cable II Driver
3. Development Kit Setup x
3.1. Default Settings 3.2. Powering Up the Development Kit 3.3. Performing Board Restore
3.3. Performing Board Restore x
3.3.1. Restoring Board QSPI Flash with Default Factory Image
4. Board Test System x
4.1. Set Up the BTS GUI Running Environment 4.2. Test the Functionality of the Development Kit 4.3. Control the On-board Clock through Clock Controller GUI 4.4. Monitor On-Board Power Regulator through Power Monitor GUI 4.5. Identify Test Pass or Fail based on BTS GUI Test Status
4.1. Set Up the BTS GUI Running Environment x
4.1.1. Downloading OpenJDK 4.1.2. Downloading OpenJFX 4.1.3. Installing OpenJDK and OpenJFX 4.1.4. Setting Up the Quartus® Prime Software for BTS Operation 4.1.5. Running the BTS GUI
4.2. Test the Functionality of the Development Kit x
4.2.1. The Bottom Information Bar 4.2.2. The Configure Menu 4.2.3. The Sys Info Tab 4.2.4. The GPIO Tab 4.2.5. The XCVR Tab 4.2.6. The Memory Tab
4.2.5. The XCVR Tab x
4.2.5.1. The QSFPDD NRZ Tab 4.2.5.2. The QSFPDD PAM4 Tab 4.2.5.3. The FMC+ NRZ Tab 4.2.5.4. The QSFPDD800 PAM4 Tab
4.2.6. The Memory Tab x
4.2.6.1. The DDR5 COMP Tab 4.2.6.2. The LP DDR5 COMP Tab 4.2.6.3. The HPS DDR5 COMP Tab 4.2.6.4. The DDR5 RDIMM Tab 4.2.6.5. The HBM2 Tab
4.2.6.5. The HBM2 Tab x
4.2.6.5.1. The HBM2 Top Tab 4.2.6.5.2. The HBM2 Bottom Tab
4.3. Control the On-board Clock through Clock Controller GUI x
4.3.1. Si5391-1 4.3.2. Si5391-2 4.3.3. Si5392 4.3.4. Si5395 4.3.5. Si5332 4.3.6. Si5518
5. Development Kit Hardware and Configuration x
5.1. Configuring FPGA and Accessing HPS Debug Access Port by JTAG 5.2. Configuring FPGA Device Using the Avalon® Streaming Interface x8 Configuration Mode 5.3. Daughter Card
5.3. Daughter Card x
5.3.1. HPS Out of Box Experience (OOBE) Daughter Card
6. Custom Projects for the Development Kit x
6.1. Add SmartVID Settings in the Quartus® Prime QSF File 6.2. Golden Top
A. Development Kit Components x
A.1. Power A.2. Clocks A.3. General Input/Output A.4. Memory Interfaces A.5. Communication Interfaces A.6. Daughter Card A.7. Connectors and Cables
C. Safety and Regulatory Compliance Information x
C.1. Safety and Regulatory Information C.2. Compliance Information
C.1. Safety and Regulatory Information x
C.1.1. Safety Warnings C.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Kit Setup
4. Board Test System
5. Development Kit Hardware and Configuration
6. Custom Projects for the Development Kit
7. Document Revision History for the Agilex™ 7 FPGA M-Series HBM2e Development Kit User Guide
A. Development Kit Components
B. Developer Resources
C. Safety and Regulatory Compliance Information

3.1. Default Settings

The Agilex™ 7 FPGA M-Series HBM2e Development Kit ships with its board switches preconfigured to support the design examples in the kit. If you suspect your board might not be correctly configured with the default settings, follow the instructions in the factory default switch settings table to return to its factory settings before proceeding ahead.

Table 4.  Factory Default Switch Settings
Note: "X" refers to Don't Care in the table below.
Note: Do not set the switches when the power is on. Only set the switches after the power is off.
Switch Default Position Notes
S24[1:4] ON/OFF/OFF/ON S24[1:3]
Set MSEL mode:
  • 111: JTAG
  • 011: Avalon® streaming interface x8 configuration mode
S24[4]:
  • OFF—FPGA can access three QSFPDD modules
  • ON—system_info_0_slv_data_write_0[2] determines if FPGA can access three QSFPDD modules or not.
    • system_info_0_slv_data_write_0[2] = 0 (by default): FPGA cannot access the modules.
    • system_info_0_slv_data_write_0[2] = 1: FPGA can access modules.
Note:

Nios® in MAX® 10 would access three QSFPDD modules for thermal control only when S24[4] set as ON and system_info_0_slv_data_write_0[2] is 0.

The FPGA can access modules when S24.4 set as OFF or S24[4] set as ON and system_info_0_slv_data_write_0[2] is 1.

system_info_0_slv_data_write_0 is a register of the MAX® 10 design and its address offset is 0x38.
S25 OFF
  • OFF—HPS is not in the JTAG chain
  • ON—HPS is in the JTAG chain
S3 OFF
  • OFF—FMC+ is not in the JTAG chain
  • ON—FMC+ is in the JTAG chain
S26 ON
  • ON— MAX® 10 programming via on-board Altera® FPGA Download Cable
  • OFF— MAX® 10 programming via external Altera® FPGA Download Cable
S28[1:4] OFF/ON/OFF/OFF

S28[1:2]

Select the clock source for EU122:
  • ON:ON—Disabled
  • OFF:ON—Internal crystal (default)
  • ON:OFF—CLKIN2 (MCIO)
  • OFF:OFF—CLKIN3 (SMP)

S28[3:4]

Set SSC:
  • ON:X—Disabled (default)
  • OFF:X—AND OUT0
  • X:ON—Disabled (default)
  • X:OFF—Enable SS on N1 divider OUT6, OUT7
S6 OFF MAX® 10 JTAG Enable switch when the JTAG pin sharing is enabled:
  • ON—JTAG pins function as dual-purpose pins
  • OFF—JTAG pins function as JTAG dedicated pins

This switch can be set to either ON or OFF with the current MAX® 10 design because the JTAG pin sharing is not enabled in the design.
S4 ON Select configuration image in the dual-configuration images mode:
  • ON—The first configuration image is configuration image 0
  • OFF—The first configuration image is configuration image 1

This switch can be set to either ON or OFF with the current MAX® 10 design because single image mode is used in the design.
S16 [1]/[0] Controls the configuration for the U35 clock device
OFF/OFF (default) Input clock from XTAL
OFF/ON Input clock from IN2
ON/OFF Input clock from IN1
ON/ON Not connected
S20 [1]/[0] Controls the configuration for the U93 clock device
OFF/OFF(default) Input clock from XTAL
OFF/ON Input clock from IN2
ON/OFF Input clock from IN1
ON/ON Not connected
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