F-Tile Triple-Speed Ethernet IP Design Example User Guide

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ID 781679
Date 9/29/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver 3. F-Tile Triple-Speed Ethernet IP Design Example User Guide Archive 4. Document Revision History for the F-Tile Triple-Speed Ethernet IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the F-Tile Triple-Speed Ethernet IP Design Example Testbench 1.4. Compiling and Configuring the Design Example in Hardware
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Test Procedure
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver
3. F-Tile Triple-Speed Ethernet IP Design Example User Guide Archive
4. Document Revision History for the F-Tile Triple-Speed Ethernet IP Design Example User Guide

2.3.1. Design Components

Table 5.  Design Components
Component Description
Triple-Speed Ethernet IP

The Triple-Speed Ethernet IP (altera_eth_tse) is instantiated with the following configuration:

  • Core Configurations:
    • Core Variation: 10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS
    • Enable ECC protection: Off
    • Interface: MII/GMII
    • Use internal FIFO: Selected
    • Number of ports: 1
    • Transceiver type: FGT
  • MAC Options:
    • Enable local loopback on MII/GMII: Not selected
    • Enable supplemental MAC unicast addresses: Not selected
    • Include statistics counters: Selected
    • Enable 64-bit statistics byte counters: Not selected
    • Include multicast hashtable: Not selected
    • Align packet headers to 32-bit boundary: Not selected
    • Enable full-duplex flow control: Not selected
    • Enable VLAN detection: Not selected
    • Enable magic packet detection: Selected
    • Include MDIO module (MDC/MDIO): Not selected
  • PCS/Transceiver Options:
    • Enable SGMII bridge: Selected
    • Enable F-Tile transceiver dynamic reconfiguration (System Clock Mode): Selected
    • System PLL Frequency: 805.664062
    • Enable datapath Avalon Interface: Selected
    • Enable PMA Avalon Interface: Selected
  • Analog Parameters Options:
    • FGT TX EQ:
      • FGT TXEQ Post Tap 1, 1.0 step size: 0
      • FGT TXEQ Main Tap, 1.0 step size: 35
      • FGT TXEQ Pre Tap 1, 1.0 step size: 5
      • FGT TXEQ Pre Tap 2, 1.0 step size: 0
    • FGT RX:
      • Select FGT RX Onchip Termination: RX_ONCHIP_TERMINATION_R_2(100 ohms)
      • Enable FGT RX On-board AC Couple: ENABLE
      • Enable FGT VSR mode: VSR_MODE_DISABLE
      • RXEQ VGA Gain: 0
      • RXEQ High Frequency Boost: 0
      • RXEQ DFE Data Tap1: 0
Client Logic Generates and monitors packets sent or received through the IP.
JTAG to Avalon® memory-mapped interface Address Decoder Convert JTAG Signals for Avalon® memory-mapped interface.
IOPLL Generates 125 MHz and 62.5 MHz clocks for Triple-Speed Ethernet.
System PLL Generates 805.664062 MHz PLL clock for FGT transceiver.
Level Two Title