AN 994: Drive-on-Chip Design Example for Intel Agilex® 7 Devices
ID
780361
Date
6/26/2023
Public
1. About the Drive-on-Chip Design Example for Intel Agilex® 7 Devices
2. Features of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3. Getting Started with the Drive-on-Chip Design Example for Intel Agilex 7 Devices
4. Rebuilding the Drive-on-Chip Design Example for Intel Agilex 7 Devices
5. About the Scaling of Feedback Signals
6. Motor Control Software
7. Functional Description of the Drive-on-Chip Design Example for Intel Agilex 7 Devices
8. Signals
9. Registers
10. Design Security Recommendations
11. Document Revision History for AN 994: Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.1. Software Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.2. Hardware Requirements for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.3. Downloading and Installing the Design
3.4. Setting Up your Development Board for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.5. Configuring the FPGA Hardware for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.6. Programming the Nios V/g Software to the Device for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.7. Debugging and Monitoring the Drive-on-Chip Design Example for Intel Agilex 7 Devices with Python GUI
3.7.1. GUI Control Parameters Pane for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.7.2. GUI Main Panes for the Drive-on-Chip Design Example for Intel Agilex 7 Devices
3.7.3. Tuning the PI Controller Gains
3.7.4. Controlling the Speed and Position Demonstrations
3.7.5. Monitoring Performance
7.3.6.1. DSP Builder for Intel FPGAs Model for the Drive-on-Chip Designs
7.3.6.2. Avalon Memory-Mapped Interface
7.3.6.3. About DSP Builder for Intel FPGAs
7.3.6.4. DSP Builder for Intel FPGAs Folding
7.3.6.5. DSP Builder for Intel FPGAs Design Guidelines
7.3.6.6. Generating VHDL for the DSP Builder Models for the Drive-on-Chip Designs
5.1. Signal Sensing in Sigma-Delta
Sigma-delta modulators on the power board model convert analog signals to a one-wire digital bitstream. The design demodulates or filters the bitstream in the FPGA. The FPGA uses two types of sigma-delta filter IP in the FPGA, ADC modules and DC link modules, each with different scaling and offset.
The design downloads and filters all sigma delta inputs in parallel so no skew exists between the samples that it feeds to the software application.
Each ADC type has a different input and output ranges with the corresponding 'C' data type.
ADC Type | Count Range | C Data type |
Sigma-delta ADC | -32768…+32767 | Signed 16-bit |
Sigma-delta DC link | 0…+32767 | Signed 16-bit |
Position feedback samples are scaled to a 23 bit unsigned integer, for consistency across all encoder types supported by this and previous Drive-on-Chip designs.
Feedback Quantity | Sigma Delta Interface IP | Sigma Delta Scaling for Tandem Motion Power Board |
---|---|---|
Motor phase voltages | ADC interface | 545 counts/V |
Motor input voltage | DC Link interface | 545 counts/V |
Motor phase currents | ADC interface | 1024 counts/A |