Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 7/08/2024
Public
Document Table of Contents

5.2. Serial Interface

The following table shows the signals of the Serial Interface of the Ethernet IP subsystem.
Table 45.  Serial Interface Signals
Signal Name Direction Description
p<n>_tx_serial[CHANNELS_PER_PORT] Out

TX serial data.

Each tx_serial bit becomes two physical pins that form a differential pair.

For 10G/25G/50GAUI-1/100GAUI-1: CHANNELS_PER_PORT=1

For 50G CAUI-2/100G CAUI-2/200GAUI-2:

CHANNELS_PER_PORT=2

For 40G CAUI-4/100G CAUI-4/200GAUI-4/400GAUI-4: CHANNELS_PER_PORT=4

For 400GAUI-8: CHANNELS_PER_PORT=8

p<n>_rx_serial[CHANNELS_PER_PORT] In

RX serial data.

Each rx_serial bit becomes two physical pins that form a differential pair.

For 10G/25G/50GAUI-1/100GAUI-1: CHANNELS_PER_PORT=1

For 50G CAUI-2/100G CAUI-2/200GAUI-2: CHANNELS_PER_PORT=2

For 40G CAUI-4/100G CAUI-4/200GAUI-4/400GAUI-4: CHANNELS_PER_PORT=4

For 400GAUI-8: CHANNELS_PER_PORT=8