Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 7/08/2024
Public
Document Table of Contents

5.1. AXI4 Interfaces

The AXI4 interfaces are named under the following convention.
  • Input to subsystem
    app_ss_<st|mm|lite>_<signal_category> p<port>_<AXI spec name><_n if 
    active low polarity>
  • Output from subsystem
    ss_app_<st|mm|lite>_<signal_category>_p<port>_<AXI spec name><_n if 
    active low polarity>