High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 773266
Date 3/18/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide 2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide 3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description 4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide x
1.1. Release Information
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide x
2.1. Creating an Quartus® Prime Project for Your HBM2E System 2.2. Configuring the High Bandwidth Memory (HBM2E) Interface FPGA IP 2.3. Generating the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example for Synthesis and Simulation 2.4. Compiling and Programming the Agilex™ 7 M-Series High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example 2.5. Using the HBM2E Design Example with the Test Engine IP 2.6. Enabling and Using the HBM2E Design Example with the Performance Monitor 2.7. Using the AXI4-Lite-enabled HBM2E Design Example in Hardware and Simulation 2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP
2.8. Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP x
2.8.1. High Bandwidth Memory (HBM2E) Interface FPGA IP Example Design For Simulation 2.8.2. Simulating High Bandwidth Memory (HBM2E) Interface FPGA IP with Synopsys VCS* 2.8.3. Simulating the HBM2E FPGA IP with ModelSim SE 2.8.4. Simulating the HBM2E FPGA IP with Cadence* Xcelium Parallel Simulator 2.8.5. Simulating High Bandwidth Memory (HBM2E) Interface IP Instantiated in Your Project
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description x
3.1. Design Example Components 3.2. Use Cases 3.3. Top-Level Signals of the HBM2E Design Example 3.4. Using the HBM2E Design Example for Performance Testing
3.2. Use Cases x
3.2.1. Initiator to Target NoC Mapping 3.2.2. Fabric NoC 3.2.3. AXI4-Lite Support
1. About the High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide
2. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Quick Start Guide
3. High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example Description
4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide

4. Document Revision History for High Bandwidth Memory (HBM2E) Interface FPGA IP Design Example User Guide

Document Version Quartus® Prime Version IP Version Changes
2025.03.18 24.3 6.0.0 In the Design Example Description chapter, updated the QSF assignment sample in the Initiator Placement section of the Using the HBM2E Design Example for Performance Testing topic.
2025.01.31 24.3 6.0.0 In the Design Example Description chapter, corrected a typo in the Design Example Components topic.
2024.11.04 24.3 6.0.0
  • In the Design Example Description chapter, added a sentence to the bottom of the Initiator Placement section in the Using the HBM2E Design Example for Performance Testing topic.
2024.04.29 24.1 4.0.0
  • In the Quick Start chapter:
    • Modified the list of supported simulators in the Simulating the High Bandwidth Memory (HBM2E) Interface FPGA IP topic.
    • Added the Using the HBM2E Design Example with the Test Engine IP topic
    • Added the Enabling and Using the HBM2E Design Example with the Performance Monitor topic.
  • In the Design Example Description chapter, modified Figure 10 in the AXI4-Lite Support topic.
2023.12.04 23.4 3.0.0
  • In the Quick Start chapter:
    • Added the Running the Test Engine IP with the HBM2E Design Example topic.
    • Added the Running the Performance Monitor with the HBM2E Design Example topic.
    • Added the Running the AXI4-Lite-enabled Design Example in Hardware and Simulation topic.
  • In the Design Example Description chapter:
    • Added a bullet point describing the performance monitor (PMON).
2023.10.02 23.3 2.0.0
  • In the Quick Start chapter:
    • Added a new step 4 to the Generating the High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example for Synthesis and Simulation topic, and updated the screenshot figure.
    • Added additional steps to the procedure in the Compiling and Programming the Intel Agilex 7 M-Series High Bandwidth Memory (HBM2E) Interface Intel FPGA IP Design Example topic.
2023.06.26 23.2 1.3.0
  • In the Design Example Description chapter, modified the figures in the AXI-Lite Support topic.
  • Minor editorial updates throughout.
2023.04.21 23.1 1.2.0 Initial release.
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