External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

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ID 772632
Date 3/31/2025
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP 4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Parameterizing the External Memory Interface for HPS IP 2.4. Configuring DQ Pin Swizzling 2.5. Generating the Synthesizable EMIF Design Example 2.6. Generating the EMIF Design Example for Simulation 2.7. Pin Placement for Agilex™ 7 M-Series EMIF IP 2.8. Compiling the Agilex™ 7 M-Series EMIF Design Example 2.9. Using the EMIF Design Example with the Test Engine IP 2.10. Generating the EMIF Design Example with the Performance Monitor
2.2. Generating and Configuring the EMIF IP x
2.2.1. Agilex™ 7 M-Series EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Timing and I/O Configuration
2.3. Parameterizing the External Memory Interface for HPS IP x
2.3.1. Parameterization Flow 2.3.2. Parametering the EMIF HPS IP 2.3.3. Parameterizing the EMIF IP
2.4. Configuring DQ Pin Swizzling x
2.4.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface 2.4.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width 2.4.3. Combining Pin and Byte Swizzling 2.4.4. Example: Swizzling for a x32 + ECC interface 2.4.5. Example: Swizzling for a 2Ch x32 + ECC interface 2.4.6. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Agilex™ 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP Design Example User Guide

2.3. Parameterizing the External Memory Interface for HPS IP

This section describes launching the EMIF IP for HPS, and provides guidance for parameterizing the IP.

To create your EMIF HPS IP, you first launch the Platform Designer, and then search for the External Memory Interfaces for HPS IP in the IP Catalog.

To launch the External Memory Interfaces for HPS IP, create a Quartus® Prime project and select an Agilex™ 7 M-Series device. Go to the Platform Designer and create a system, then click IP catalog > Processors and Peripherals > Hard Processor Components > Hard Processor Components > xternal Memory Interfaces for HPS IP.

To launch the External Memory Interfaces for HPS IP, follow these steps:

  1. Create a Quartus® Prime project and select an Agilex™ 7 M-Series device.
  2. Go to the Platform Designer and create a system.
  3. Click IP catalog > Processors and Peripherals > Hard Processor Components > Hard Processor Components > xternal Memory Interfaces for HPS IP.

The preceeding steps open the External Memory Interfaces for HPS IP parameter editor, where you can set high-level parameters for your interface.

Figure 12. Launching the External Memory Interfaces for HPS IP Parameter Editor

Click to instantiate the External Memory Interfaces for HPS IP in your Platform Designer system.


Section Content
Parameterization Flow
Parametering the EMIF HPS IP
Parameterizing the EMIF IP

Level Two Title