2.5. Generating the EMIF Design Example for Simulation
- On the Example Designs tab, ensure that the Simulation box is set as True. Also choose the required Simulation HDL format, either Verilog or VHDL.
- Configure the EMIF IP and click File > Save to save the current setting into the user IP variation file (<user instance name>.ip).
- Click Generate Example Design in the upper-right corner of the window.
Figure 32. Generate Example Design
- Specify a directory for the EMIF design example and click OK. Successful generation of the EMIF design example creates multiple file sets for various supported simulators, under a sim/ed_sim directory.
Figure 33. Specifying a Directory
- Click File > Exit to exit the IP Parameter Editor Pro window. The system prompts, Recent changes have not been generated. Generate now? Click No to continue with the next flow.
Figure 34. Generated Simulation Design Example File StructureNote: The External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP currently supports only the VCS, ModelSim/QuestaSim, and Xcelium simulators.
If you don't select the Simulation or Synthesis checkbox, the destination directory contains only Platform Designer design files, which the Intel® Quartus® Prime software cannot compile directly, but which you can view or edit in the Platform Designer. In this situation you can run the following commands to generate synthesis and simulation file sets:
- To create an Intel® Quartus® Prime software-compilable project, run the
quartus_sh -t make_qii_design.tclscript in the destination directory.
- To create a simulation project, run the
quartus_sh -t make_sim_design.tclscript in the destination directory.