External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

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ID 772538
Date 7/07/2025
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction 3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture 4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals 5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support 7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support 8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure 10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization 11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging 12. Agilex™ 7 FPGA EMIF IP - Mailbox Support 13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction x
2.1. Agilex™ 7 M-Series EMIF IP Protocol and Feature Support 2.2. Agilex™ 7 M-Series EMIF IP Design Flow 2.3. Agilex™ 7 M-Series EMIF IP Design Checklist
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction 3.2. Agilex™ 7 M-Series EMIF Sequencer 3.3. Agilex™ 7 M-Series EMIF Controller 3.4. Agilex™ 7 M-Series EMIF IP Interface Protocol: Interface Width, User Access Mode, and ECC 3.5. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction x
3.1.1. Agilex™ 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Agilex™ 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Agilex™ 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Agilex™ 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Agilex™ 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Agilex™ 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Agilex™ 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. I/O Byte Lane Organization in Different Agilex™ 7 M-Series Devices 3.1.3.2. Lockstep Configuration 3.1.3.3. DDR4 Pin Placement 3.1.3.4. DDR5 Pin Placement 3.1.3.5. LPDDR5 Pin Placement 3.1.3.6. I/O Sub-Bank Usage
3.3. Agilex™ 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
3.5. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS) x
3.5.1. Restrictions on I/O Bank Usage for Agilex™ 7 M-Series EMIF IP with HPS
3.5.1. Restrictions on I/O Bank Usage for Agilex™ 7 M-Series EMIF IP with HPS x
3.5.1.1. Using the Legacy EMIF Debug Toolkit with Agilex™ 7 M-Series HPS Interfaces
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.3. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.4. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.5. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.13. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM x
4.2.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.4. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.5. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.6. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.7. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.8. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.9. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.10. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.11. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.12. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.13. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 DIMM
4.3. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component x
4.3.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.4. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.5. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.6. s1_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.7. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.8. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.9. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.10. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.11. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.12. mem_reset_n_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.13. mem_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.14. mem_ck_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.15. mem_reset_n_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.16. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.17. oct_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.18. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component
4.4. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM x
4.4.1. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.2. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.3. s1_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.4. s1_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.5. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.6. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.7. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.8. s1_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.9. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.10. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.11. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.12. s1_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.13. s1_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.14. s1_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.15. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.16. mem_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.17. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.18. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.19. mem_ck_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.20. mem_i3c for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.21. mem_lb_dq for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.22. mem_lb_dqs for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.23. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.24. oct_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.25. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 DIMM
4.5. IP Interfaces for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 x
4.5.1. s0_axi4_clock_in for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.2. core_init_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.3. s0_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.4. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.5. s1_axi4_ctrl_ready for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.6. s1_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.7. s0_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.8. s1_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.9. s2_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.10. s3_axi4 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.11. s0_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.12. s0_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.13. s0_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.14. s1_axi4lite_clock for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.15. s1_axi4lite_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.16. s1_axi4lite for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.17. mem_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.18. mem_ck_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.19. mem_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.20. mem_ck_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.21. mem_2 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.22. mem_ck_2 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.23. mem_3 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.24. mem_ck_3 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.25. mem_reset_n for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.26. oct_0 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.27. oct_1 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.28. oct_2 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.29. oct_3 for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5 4.5.30. ref_clk for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example 5.1.5. Simulating with sim_lib2
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. Agilex 7 M-Series DDR4 Component External Memory Interfaces (EMIF) IP Parameter Descriptions 6.2. Agilex 7 M-Series DDR4 DIMM External Memory Interfaces (EMIF) IP Parameter Descriptions 6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.4. DDR4 Board Design Guidelines
6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 6.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
6.3.1.1. Estimating Pin Requirements 6.3.1.2. DIMM Options 6.3.1.3. Maximum Number of Interfaces
6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
6.3.2.1. OCT 6.3.2.2. PLL
6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP x
6.3.4.1. Address and Command Pin Placement for DDR4 6.3.4.2. DDR4 Data Width Mapping 6.3.4.3. General Guidelines - DDR4 6.3.4.4. x4 DIMM Implementation 6.3.4.5. Specific Pin Connection Requirements 6.3.4.6. Command and Address Signals 6.3.4.7. Clock Signals 6.3.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. DDR4 Board Design Guidelines x
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices 6.4.2. General Layout Routing Guidelines 6.4.3. Reference Stackup 6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices x
6.4.1.1. Dynamic On-Chip Termination (OCT) 6.4.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.4.1.3. Choosing Terminations on Agilex™ 7 M-Series FPGA Devices 6.4.1.4. On-Chip Termination Recommendations for Agilex™ 7 M-Series FPGA Devices
6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.4.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.4.4.2. Skew Matching Guidelines for DIMM Configurations 6.4.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.4.5.1. Single Rank and Dual Rank x 8 Discrete (Component) Topology 6.4.5.2. Single Rank x16 and Dual Rank x16 Discrete (Component) Topology 6.4.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.4.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.4.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
6.4.5.6.1. DDR4 Byte Lane Swapping 6.4.5.6.2. DDR4 Address and Command and CLK Lane 6.4.5.6.3. DDR4 Interface x8 Data Lane 6.4.5.6.4. DDR4 Interface x4 Data Lane 6.4.5.6.5. Pin Swizzling
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. Agilex 7 M-Series DDR5 Component External Memory Interfaces (EMIF) IP Parameter Descriptions 7.2. Agilex 7 M-Series DDR5 DIMM External Memory Interfaces (EMIF) IP Parameter Descriptions 7.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.4. DDR5 Board Design Guidelines
7.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 7.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 7.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 7.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP 7.3.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
7.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. DIMM Options 7.3.1.3. Maximum Number of Interfaces
7.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
7.3.3.1. General Guidelines - DDR5 7.3.3.2. x4 DIMM Implementation 7.3.3.3. Specific Pin Connection Requirements 7.3.3.4. Command and Address Signals 7.3.3.5. Clock Signals 7.3.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP x
7.3.4.1. Address and Command Pin Placement for DDR5 7.3.4.2. DDR5 Data Width Mapping
7.3.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
7.3.5.1. DDR5 Byte Lane Swapping 7.3.5.2. DDR5 Address and Command and CLK Lane 7.3.5.3. DDR5 Interface x8 Data Lane 7.3.5.4. DDR5 Interface x4 Data Lane 7.3.5.5. Pin Swizzling
7.4. DDR5 Board Design Guidelines x
7.4.1. PCB Stack-up and Design Considerations 7.4.2. General Design Considerations 7.4.3. DDR Differential Signals Routing 7.4.4. Ground Plane and Return Path 7.4.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.4.6. DRAM Break-in Layout Guidelines 7.4.7. General Notes for EMIF Routing Guidelines Tables 7.4.8. DDR5 PCB Layout Guidelines 7.4.9. DDR5 RDIMM Power Management IC 7.4.10. DDR5 Simulation Strategy
7.4.8. DDR5 PCB Layout Guidelines x
7.4.8.1. DDR5 Discrete Component/Memory Down Topology: Single Rank x8 or x16, Dual Rank x8 or x16 7.4.8.2. Routing Guidelines for DDR5 Memory Down: Single Rank or Dual Rank (x8 bit or x16 bit) Configurations 7.4.8.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.4.8.4. Example of a DDR5 layout on an Altera FPGA Platform Board
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. Agilex 7 M-Series LPDDR5 External Memory Interfaces (EMIF) IP Parameter Descriptions 8.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.3. LPDDR5 Board Design Guidelines
8.2. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 8.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 8.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 8.2.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP
8.2.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
8.2.1.1. Estimating Pin Requirements 8.2.1.2. LPDDR5 Component Options 8.2.1.3. Maximum Number of Interfaces
8.2.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
8.2.2.1. OCT 8.2.2.2. PLL
8.2.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
8.2.3.1. General Guidelines - LPDDR5 8.2.3.2. Specific Pin Connection Requirements 8.2.3.3. Command and Address Signals 8.2.3.4. Clock Signals
8.2.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP x
8.2.4.1. Address and Command Pin Placement for LPDDR5 8.2.4.2. LPDDR5 Data Width Mapping 8.2.4.3. LPDDR5 Byte Lane Swapping
8.3. LPDDR5 Board Design Guidelines x
8.3.1. PCB Stack-up and Design Considerations 8.3.2. General Design Considerations 8.3.3. DDR Differential Signals Routing 8.3.4. Ground Plane and Return Path 8.3.5. DRAM Break-in Layout Guidelines 8.3.6. General Notes for EMIF Routing Guidelines Tables 8.3.7. LPDDR5 PCB Layout Guidelines 8.3.8. LPDDR5 Simulation Strategy
8.3.7. LPDDR5 PCB Layout Guidelines x
8.3.7.1. LPDDR5 Discrete Component/Memory Down Topology, Single Rank or Dual Rank 8.3.7.2. Routing Guidelines for LPDDR5 Memory Down Topology 8.3.7.3. Example of an LPDDR5 Layout on an Altera® FPGA Platform Board
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. Optimizing Efficiency for Secondary Controller 10.2. Interface Standard 10.3. Bank Management Efficiency 10.4. Data Transfer 10.5. Improving Controller Efficiency
10.5. Improving Controller Efficiency x
10.5.1. Using Multiple AXI IDs 10.5.2. Controller Performance Profile 10.5.3. Frequency of Operation 10.5.4. Series of Reads or Writes 10.5.5. AXI to Memory Mapping
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Debugging with the External Memory Interface Debug Toolkit 11.6. Generating Traffic with the Test Engine IP 11.7. Guidelines for Developing HDL for Traffic Generator 11.8. Guidelines for Traffic Generator Status Check 11.9. Hardware Debugging Guidelines 11.10. Categorizing Hardware Issues 11.11. Debugging Intermittent Issues
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Altera IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.5. Debugging with the External Memory Interface Debug Toolkit x
11.5.1. Prerequisites for Using the EMIF Debug Toolkit 11.5.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.5.3. Launching the EMIF Debug Toolkit 11.5.4. Using the EMIF Debug Toolkit
11.5.4. Using the EMIF Debug Toolkit x
11.5.4.1. Rerunning Calibration 11.5.4.2. Rerunning the Test Engine 11.5.4.3. Saving Debug Print 11.5.4.4. Calibration Reports 11.5.4.5. Driver Margining Tab 11.5.4.6. Pin Delay Settings Tab
11.8. Guidelines for Traffic Generator Status Check x
11.8.1. Status Check Using the Signal Tap Logic Analyzer 11.8.2. Exporting the Status Interface to the Top-Level Design
11.9. Hardware Debugging Guidelines x
11.9.1. Create a Simplified Design that Demonstrates the Same Issue 11.9.2. Measure Power Distribution Network 11.9.3. Measure Signal Integrity and Setup and Hold Margin 11.9.4. Vary Voltage 11.9.5. Operate at a Lower Speed 11.9.6. Determine Whether the Issue Exists in Previous Versions of Software 11.9.7. Determine Whether the Issue Exists in the Current Version of Software 11.9.8. Try A Different PCB 11.9.9. Try Other Configurations 11.9.10. Debugging Checklist
11.10. Categorizing Hardware Issues x
11.10.1. Signal Integrity Issues 11.10.2. Hardware and Calibration Issues
11.10.1. Signal Integrity Issues x
11.10.1.1. Characteristics of Signal Integrity Issues 11.10.1.2. Evaluating Signal Integrity Issues
11.10.1.2. Evaluating Signal Integrity Issues x
11.10.1.2.1. Skew 11.10.1.2.2. Crosstalk 11.10.1.2.3. Power System 11.10.1.2.4. Clock Signals 11.10.1.2.5. Address and Command Signals 11.10.1.2.6. Read Data Valid Window and Eye Diagram 11.10.1.2.7. Write Data Valid Window and Eye Diagram
11.10.2. Hardware and Calibration Issues x
11.10.2.1. Verifying High-Level Configuration 11.10.2.2. Verifying Memory Timing Parameters 11.10.2.3. Verifying the Correct Memory Component or DIMM is Installed
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support x
12.1. Agilex™ 7 Mailbox Structure and Register Definitions
12.1. Agilex™ 7 Mailbox Structure and Register Definitions x
12.1.1. Mailbox Supported Commands 12.1.2. Mailbox Command Definitions 12.1.3. ECC Syndrome Codes 12.1.4. ECC Error Handling 12.1.5. Accessing Read-Only Registers 12.1.6. Sending a Mailbox Command 12.1.7. IOSSM Mailbox Access Script
12.1.5. Accessing Read-Only Registers x
12.1.5.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Through Read-Only Registers 12.1.5.2. Example 2: Reading the Memory Clock Frequency for an Interface
12.1.6. Sending a Mailbox Command x
12.1.6.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
12.1.6.1. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox x
12.1.6.1.1. Example 4: Sending ECC_INJECT_ERROR Using the Mailbox and Reading ECC Error Status, ECC Error Buffer Registers
12.1.7. IOSSM Mailbox Access Script x
12.1.7.1. Mailbox Script Overview 12.1.7.2. Running the Mailbox Script
12.1.7.1. Mailbox Script Overview x
12.1.7.1.1. mb_iossm_command.tcl 12.1.7.1.2. mb_user_input.tcl
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support
13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

7.2. Agilex 7 M-Series DDR5 DIMM External Memory Interfaces (EMIF) IP Parameter Descriptions

The following tables describe the parameters available on each tab of the IP parameter editor, which you can use to configure your IP.
Table 185.  Group: High-level Configuration / Memory Device
Parameter Name Description
DIMM Type

Specifies the type of DIMM that is used with this interface.

Default value is UDIMM

Legal values are: UDIMM, SODIMM, RDIMM

(Identifier: MEM_DIMM_TYPE)
Data DQ Width

Number of DQ pins per memory channel, used for data.

Default value is 32

Legal values are: 32, 40

(Identifier: MEM_CHANNEL_DATA_DQ_WIDTH)
ECC DQ Width

Number of additional DQ pins per memory channel, used for out-of-band ECC. If bigger than 0, controller will enable out-of-band ECC. Otherwise, out-of-band ECC will be disabled.

Default value is 4

Legal values are: 0, 4, 8

(Identifier: MEM_CHANNEL_ECC_DQ_WIDTH)
Die DQ Width

Number of DQ pins in each die that makes up the interface. For dual-die packages, this is the width of the die, not the width of full the package.

Default value is 8

Legal values are: 4, 8, 16

(Identifier: MEM_DIE_DQ_WIDTH)
Die Density

Capacity of each memory die (in Gbits), per channel per die. For dual-die packages, this is the density of each die, not the density of the full package.

Default value is 8

Legal values are:

  • 8Gbits (8)
  • 16Gbits (16)
  • 24Gbits (24)
  • 32Gbits (32)

(Identifier: MEM_DIE_DENSITY_GBITS)
CS Width

Specifies the total number of CS pins used by each channel.

Default value is 1

Legal values are: 1, 2

(Identifier: MEM_CHANNEL_CS_WIDTH)
Memory Speedbin

Specifies the speedbin of the memory device(s) of which the interface consists.

Default value is 5600AN

Legal values are:

  • 3200AN (CL24) (3200AN)
  • 3200B (CL26) (3200B)
  • 3200BN (CL26) (3200BN)
  • 3200C (CL28) (3200C)
  • 3600AN (CL26) (3600AN)
  • 3600B (CL30) (3600B)
  • 3600BN (CL30) (3600BN)
  • 3600C (CL32) (3600C)
  • 4000AN (CL28) (4000AN)
  • 4000B (CL32) (4000B)
  • 4000BN (CL32) (4000BN)
  • 4000C (CL36) (4000C)
  • 4400AN (CL32) (4400AN)
  • 4400B (CL36) (4400B)
  • 4400BN (CL36) (4400BN)
  • 4400C (CL40) (4400C)
  • 4800AN (CL34) (4800AN)
  • 4800B (CL40) (4800B)
  • 4800BN (CL40) (4800BN)
  • 4800C (CL42) (4800C)
  • 5200AN (CL38) (5200AN)
  • 5200B (CL42) (5200B)
  • 5200BN (CL42) (5200BN)
  • 5200C (CL46) (5200C)
  • 5600AN (CL40) (5600AN)
  • 5600B (CL46) (5600B)
  • 5600BN (CL46) (5600BN)
  • 5600C (CL50) (5600C)
  • 3DS_3200AN (CL26) (3DS_3200AN)
  • 3DS_3200B (CL30) (3DS_3200B)
  • 3DS_3200BN (CL30) (3DS_3200BN)
  • 3DS_3200C (CL32) (3DS_3200C)
  • 3DS_3600AN (CL30) (3DS_3600AN)
  • 3DS_3600B (CL34) (3DS_3600B)
  • 3DS_3600BN (CL34) (3DS_3600BN)
  • 3DS_3600C (CL36) (3DS_3600C)
  • 3DS_4000AN (CL32) (3DS_4000AN)
  • 3DS_4000B (CL38) (3DS_4000B)
  • 3DS_4000BN (CL38) (3DS_4000BN)
  • 3DS_4000C (CL40) (3DS_4000C)
  • 3DS_4400AN (CL36) (3DS_4400AN)
  • 3DS_4400B (CL42) (3DS_4400B)
  • 3DS_4400BN (CL42) (3DS_4400BN)
  • 3DS_4400C (CL44) (3DS_4400C)
  • 3DS_4800AN (CL40) (3DS_4800AN)
  • 3DS_4800B (CL46) (3DS_4800B)
  • 3DS_4800BN (CL46) (3DS_4800BN)
  • 3DS_4800C (CL48) (3DS_4800C)
  • 3DS_5200AN (CL42) (3DS_5200AN)
  • 3DS_5200B (CL50) (3DS_5200B)
  • 3DS_5200BN (CL50) (3DS_5200BN)
  • 3DS_5200C (CL52) (3DS_5200C)
  • 3DS_5600AN (CL46) (3DS_5600AN)
  • 3DS_5600B (CL52) (3DS_5600B)
  • 3DS_5600BN (CL52) (3DS_5600BN)
  • 3DS_5600C (CL56) (3DS_5600C)

(Identifier: MEM_SPEEDBIN)
Auto-set Memory Operating Frequency

If true, let IP select max frequency that this configuration can support for the current device speedgrade. If false, user can set custom value for operating frequency.

Default value is true

(Identifier: MEM_OPERATING_FREQ_MHZ_AUTOSET_EN)
Memory Operating Frequency

Specifies the frequency at which the memory interface will run.

Value is specified in megahertz

Legal values are: 1600, 1800, 2000, 2200, 2400, 2600, 2800

(Identifier: MEM_OPERATING_FREQ_MHZ)
Table 186.  Group: High-level Configuration / PHY
Parameter Name Description
Auto-set PLL Reference Clock Frequency

If true, let IP select max PLL refclk frequency that this configuration can support. If false, user can set custom value for PLL refclk frequency.

Default value is true

(Identifier: PHY_REFCLK_FREQ_MHZ_AUTOSET_EN)
Enable Advanced List of PLL Reference Clock Frequencies

If true, provide extended list of possible refclk values. Otherwise, prune possible list of refclk values to a more reasonable length.

Default value is false

(Identifier: PHY_REFCLK_ADVANCED_SELECT_EN)
Reference Clock Frequency

Specifies the reference clock frequency for the EMIF IOPLL.

Value is specified in megahertz

(Identifier: PHY_REFCLK_FREQ_MHZ)
AC Placement

Indicates location on the device where the interface will reside (specifically, the location of the AC lanes in terms I/O BANK and TOP vs BOT part of the I/O BANK). Legal ranges are derived from device floorplan.

Default value is BOT_BOT

Legal values are:

  • Ch0 Bot Sub-Bank / Ch1 Top Sub-Bank (BOT_TOP)
  • Ch0 Top Sub-Bank / Ch1 Bot Sub-Bank (TOP_BOT)
  • Ch0 Bot Sub-Bank / Ch1 Bot Sub-Bank (BOT_BOT)

(Identifier: PHY_AC_PLACEMENT)
Auto-set Mainband Access Mode

If true, let IP select most likely usecase for the PHY_MAINBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode.

Default value is true

(Identifier: PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN)
Mainband Access Mode

Specifies the path through which the EMIF QHIP mainband interface is exposed to the user. The mainband interface is the AXI4 interface to the memory controller.

Legal values are:

  • NoC (NOC)
  • Fabric Direct - User Clock Asynchronous to PHY (ASYNC)
  • Fabric Direct - User Clock Synchronous to PHY (SYNC)

(Identifier: PHY_MAINBAND_ACCESS_MODE)
Auto-set Sideband Access Mode

If true, let IP select most likely usecase for the PHY_SIDEBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode.

Default value is true

(Identifier: PHY_SIDEBAND_ACCESS_MODE_AUTOSET_EN)
Sideband Access Mode

Specifies the path through which the EMIF QHIP sideband interface is exposed to the user. The sideband interface is the AXI4-Lite interface to the IOSSM.

Legal values are:

  • NoC (NOC)
  • Fabric Direct (FABRIC)

(Identifier: PHY_SIDEBAND_ACCESS_MODE)
Pin Swizzle Map

Specifies the swizzle map for the data lanes and pins.

(Identifier: PHY_SWIZZLE_MAP)
Use Debug Toolkit

If enabled, the AXI-L port will be connected to SLD nodes, allowing for a system-console avalon manager interface to interact with this AXI-L subordinate interface.

Default value is false

(Identifier: DEBUG_TOOLS_EN)
Instance ID

Instance ID of the EMIF IP. This is useful when using a discovery mechanism over the side-band interface, to identify which EMIF instance's mailbox is at which offset. If expecting to use a discovery mechanism in hardware, this parameter must be set uniquely for all EMIFs that share a sideband. Otherwise, this parameter can be ignored / kept at the default value.

Default value is 0

Legal values are: from 0 to 6

(Identifier: INSTANCE_ID)
Table 187.  Group: High-level Configuration / Controller / Controller Options
Parameter Name Description
Use ECC Autocorrection

If ECC is enabled, specifies whether single-bit-errors (SBEs) should be corrected or just reported.

Default value is true

(Identifier: CTRL_ECC_AUTOCORRECT_EN)
Use Data Masking

Specifies whether Data Masking is enabled by the controller. When ECC is enabled, RMWs will occur (to recompute / write ECC), regardless of whether this is enabled.

Default value is false

(Identifier: CTRL_DM_EN)
Controller Performance Profile

Group of Controller settings to optimize performance based on expected traffic patterns. Choose "Custom" for fine-granular control

Default value is SEQ

Legal values are:

  • Sequential Access Optimized (SEQ)
  • Random Access Optimized (RAND)
  • Custom (CUSTOM)

(Identifier: CTRL_PERFORMANCE_PROFILE)
Force Auto-Precharge

Controller will terminate all transactions with an auto-precharge when enabled. For per-transaction granularity, leave this option disabled and use the AxUSER control signals instead.

Default value is false

(Identifier: CTRL_AUTO_PRECHARGE_EN)
Bank Group Rotation

Moves a number of Bank Group pins lower in the address order

Default value is 2

Legal values are:

  • No BGs (disabled) (0)
  • Two BGs (BG[0]) (1)
  • Four BGs (BG[1:0]) (2)
  • Eight BGs (BG[2:0]) (3)

(Identifier: CTRL_BG_ROTATE_EN)
Enable Row/CS Swap

Specifies whether the highest order address bits are the CS bit (false) or Row bits (true)

Default value is false

(Identifier: DIAG_HMC_ADDR_SWAP_EN)
Table 188.  Group: High-level Configuration / Controller / Data Bus Turnaround Times
Parameter Name Description
Additional read-to-write turnaround time (same rank)

Additional memory clock cycles of delay between read and write operations within the same rank

Value is specified in Cycles

Default value is 0

Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16

(Identifier: TURNAROUND_R2W_SAMECS_CYC)
Additional read-to-read turnaround time (same rank)

Additional memory clock cycles of delay between read operations within the same rank

Value is specified in Cycles

Default value is 0

Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16

(Identifier: TURNAROUND_R2R_SAMECS_CYC)
Additional write-to-write turnaround time (same rank)

Additional memory clock cycles of delay between write operations within the same rank

Value is specified in Cycles

Default value is 0

Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16

(Identifier: TURNAROUND_W2W_SAMECS_CYC)
Additional write-to-read turnaround time (same rank)

Additional memory clock cycles of delay between read and write operations within the same rank

Value is specified in Cycles

Default value is 0

Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16

(Identifier: TURNAROUND_W2R_SAMECS_CYC)
Additional read-to-write turnaround time (different ranks)

Additional controller cycles of delay between read and write operations across different ranks

Value is specified in Cycles

Default value is 0

Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16

(Identifier: TURNAROUND_R2W_DIFFCS_CYC)
Additional read-to-read turnaround time (different ranks)

Additional controller cycles of delay between read operations across different ranks

Value is specified in Cycles

Default value is 0

Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16

(Identifier: TURNAROUND_R2R_DIFFCS_CYC)
Additional write-to-write turnaround time (different ranks)

Additional controller cycles of delay between write operations across different ranks

Value is specified in Cycles

Default value is 0

Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16

(Identifier: TURNAROUND_W2W_DIFFCS_CYC)
Additional write-to-read turnaround time (different ranks)

Additional controller cycles of delay between write and read operations across different ranks

Value is specified in Cycles

Default value is 0

Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16

(Identifier: TURNAROUND_W2R_DIFFCS_CYC)
Table 189.  Group: High-level Configuration / Advanced Calibration Settings
Parameter Name Description
Enable Margining during Calibration

Enable margining stages of calibration for use with the EMIF Debug Toolkit. This will increase calibration time

Default value is false

(Identifier: ADV_CAL_ENABLE_MARGIN)
Enable REQ Calibration

Enable the Read DQ Equalization stage as part of calibration. This will increase calibration time but will also improve top-line performance

Default value is false

(Identifier: ADV_CAL_ENABLE_REQ)
Enable WEQ Calibration

Run the Write DQ Equalization stage as part of calibration. This will increase calibration time but will also improve top-line performance

Default value is false

(Identifier: ADV_CAL_ENABLE_WEQ)
Enable Read DFE Training

Enable DFE training as part of calibration

Default value is false

(Identifier: ADV_CAL_ENABLE_RD_DFE)
Enable Write DFE Training

Enable DFE training as part of calibration

Default value is false

(Identifier: ADV_CAL_ENABLE_WR_DFE)
Table 190.  Group: Advanced: Memory Timing / Overrides / JEDEC_TABLE
Parameter Name Description
JEDEC Parameter

Name of JEDEC Parameter to explicitly override; the values will be applied and appear in the list below.

Default value is

Legal values are:

  • Operating Speedbin (MEM_OPERATING_SPEEDBIN)
  • Read Latency (MEM_CL_CYC)
  • Write Latency (MEM_CWL_CYC)
  • Write Preamble Mode (MEM_WR_PREAMBLE_MODE)
  • Read Preamble Mode (MEM_RD_PREAMBLE_MODE)
  • Write Postamble Mode (MEM_WR_POSTAMBLE_MODE)
  • Read Postamble Mode (MEM_RD_POSTAMBLE_MODE)
  • Memory Fine Granularity Refresh Mode (MEM_FINE_GRANULARITY_REFRESH_MODE)
  • tREFI1 (MEM_TREFI1_NS)
  • tREFI2 (MEM_TREFI2_NS)
  • tREFISB (MEM_TREFISB_NS)
  • tCCD_S (MEM_TCCD_S_CYC)
  • tCCD_L (MEM_TCCD_L_NS)
  • tCCD_L_WR (MEM_TCCD_L_WR_NS)
  • tCCD_L_WR2 (MEM_TCCD_L_WR2_NS)
  • tRRD_S (MEM_TRRD_S_CYC)
  • tRRD_L (MEM_TRRD_L_NS)
  • tFAW (MEM_TFAW_NS)
  • tRFC1 (MEM_TRFC1_NS)
  • tRFC2 (MEM_TRFC2_NS)
  • tRFCSB (MEM_TRFCSB_NS)
  • tRCD (MEM_TRCD_NS)
  • tRP (MEM_TRP_NS)
  • tRAS (MEM_TRAS_NS)
  • tRC (tRAS+tRP) (MEM_TRC_NS)
  • tREFSBRD (MEM_TREFSBRD_NS)
  • tWR (MEM_TWR_NS)
  • tZQLAT (MEM_TZQLAT_NS)
  • tZQCAL (MEM_TZQCAL_NS)
  • tMRR (MEM_TMRR_NS)
  • tMRR_P (MEM_TMRR_P_NS)
  • tMRW (MEM_TMRW_NS)
  • tMRD (MEM_TMRD_NS)
  • tDFE (MEM_TDFE_NS)
  • tDLLK (MEM_TDLLK_NS)
  • tWTR_S (MEM_TWTR_S_NS)
  • tWTR_L (MEM_TWTR_L_NS)
  • tRTP (MEM_TRTP_NS)
  • tPPD (MEM_TPPD_CYC)
  • tPD (MEM_TPD_NS)
  • tACTPDEN (MEM_TACTPDEN_CYC)
  • tPRPDEN (MEM_TPRPDEN_CYC)
  • tREFPDEN (MEM_TREFPDEN_CYC)
  • tXP (MEM_TXP_NS)
  • tCPDED (MEM_TCPDED_CYC)
  • tCSL (MEM_TCSL_NS)
  • tCKSRX (MEM_TCKSRX_NS)
  • tCSH_SREXIT (MEM_TCSH_SREXIT_NS)
  • tDQSCK_MIN (MEM_TDQSCK_MIN_CYC)
  • tDQSCK_MAX (MEM_TDQSCK_MAX_CYC)
  • tDQSCK (MEM_TDQSCK_CYC)
  • tWPRE_EN (MEM_TWPRE_EN_CYC)
  • tDQSS (MEM_TDQSS_CYC)
  • tCKLCS (MEM_TCKLCS_CYC)
  • tWTRA (MEM_TWTRA_NS)
  • RDIMM Serial Presence Detect (SPD) Byte 248 (MEM_SPD248_CK_CONTROL_ENABLE)
  • RDIMM Serial Presence Detect (SPD) Byte 249 (MEM_SPD249_QCA_CS_ENABLE)
  • RDIMM Serial Presence Detect (SPD) Byte 250 (MEM_SPD250_QCK_SIGNAL_DRIVER_STRENGTH)
  • RDIMM Serial Presence Detect (SPD) Byte 252 (MEM_SPD252_QCA_QCS_SIGNAL_DRIVER_STRENGTH)
  • RDIMM Serial Presence Detect (SPD) Byte 254 (MEM_SPD254_CK_CA_CS_SLEW_RATE)
  • tRRD_DLR (MEM_TRRD_DLR_NS)
  • tFAW_DLR (MEM_TFAW_DLR_NS)
  • tCCD_DLR (MEM_TCCD_DLR_NS)

(Identifier: JEDEC_OVERRIDE_TABLE_PARAM_NAME)
Table 191.  Group: Advanced: Memory Timing / Values
Parameter Name Description
Operating Speedbin

Specifies the operating speedbin of the memory device(s) for the current operating frequency and device speedbin.

(Identifier: MEM_OPERATING_SPEEDBIN)
Read Latency

Read Latency of the memory device in clock cycles.

(Identifier: MEM_CL_CYC)
Write Latency

Write Latency in clock cycles.

(Identifier: MEM_CWL_CYC)
Write Preamble Mode

Specifies the write preamble mode of the memory inteface (0: not supported, 1: 2-cycle preamble, 2: 3-cycle preamble, 3: 4-cycle preamble).

(Identifier: MEM_WR_PREAMBLE_MODE)
Read Preamble Mode

Specifies the read preamble mode of the memory inteface (0: 1-cycle preamble, 1: 2-cycle preamble, 2: 2-cycle DDR4-style preamble, 3: 3-cycle preamble, 4: 4-cycle preamble).

(Identifier: MEM_RD_PREAMBLE_MODE)
Write Postamble Mode

Specifies the write postamble mode of the memory inteface (0: 0.5-cycle postamble, 1: 1.5-cycle postamble).

(Identifier: MEM_WR_POSTAMBLE_MODE)
Read Postamble Mode

Specifies the read postamble mode of the memory inteface (0: 0.5-tCK postamble, 1: 1.5-tCK postamble).

(Identifier: MEM_RD_POSTAMBLE_MODE)
Memory Fine Granularity Refresh Mode

Specifies the Fine Granularity Refresh (FGR) mode of the memory interface.

(Identifier: MEM_FINE_GRANULARITY_REFRESH_MODE)
tREFI1

Specifies the maximum average refresh interval in normal refresh mode in nanoseconds.

(Identifier: MEM_TREFI1_NS)
tREFI2

Specifies the maximum average refresh interval in fine granularity refresh mode in nanoseconds.

(Identifier: MEM_TREFI2_NS)
tREFISB

Specifies the maximum average refresh interval in fine granularity and same bank refresh mode in nanoseconds.

(Identifier: MEM_TREFISB_NS)
tCCD_S

Specifies the CAS_n to CAS_n command delay for different bank group in cycles.

(Identifier: MEM_TCCD_S_CYC)
tCCD_L

Specifies the CAS_n to CAS_n command delay for same bank group in nanoseconds.

(Identifier: MEM_TCCD_L_NS)
tCCD_L_WR

Specifies the write CAS_n to write CAS_n command delay for same bank group in nanoseconds.

(Identifier: MEM_TCCD_L_WR_NS)
tCCD_L_WR2

Specifies the write CAS_n to write CAS_n command delay for same bank group and the second write is not RMW, in nanoseconds.

(Identifier: MEM_TCCD_L_WR2_NS)
tRRD_S

Specifies the Activate-to-Activate command delay to different bank group for 1KB page size in cycles.

(Identifier: MEM_TRRD_S_CYC)
tRRD_L

Specifies the Activate-to-Activate command delay to same bank group for 1KB page size in nanoseconds.

(Identifier: MEM_TRRD_L_NS)
tFAW

Specifies the four activate window for 1KB page size in nanoseconds.

(Identifier: MEM_TFAW_NS)
tRFC1

Specifies the refresh operation delay in normal refresh mode in nanoseconds.

(Identifier: MEM_TRFC1_NS)
tRFC2

Specifies the refresh operation delay in fine granularity refresh mode in nanoseconds.

(Identifier: MEM_TRFC2_NS)
tRFCSB

Specifies the refresh operation delay in fine granularity and same bank refresh mode in nanoseconds.

(Identifier: MEM_TRFCSB_NS)
tRCD

Specifies the Activate-to-internal-Read-or-Write delay in nanoseconds.

(Identifier: MEM_TRCD_NS)
tRP

Specifies the row precharge time in nanoseconds.

(Identifier: MEM_TRP_NS)
tRAS

Specifies the Activate-to-Precharge command period in nanoseconds.

(Identifier: MEM_TRAS_NS)
tRC (tRAS+tRP)

Specifies the Activate-to-Activate or Refresh command period in nanoseconds.

(Identifier: MEM_TRC_NS)
tREFSBRD

Specifies the same bank refresh to activate delay in nanoseconds.

(Identifier: MEM_TREFSBRD_NS)
tWR

Specifies the write recovery time in nanoseconds.

(Identifier: MEM_TWR_NS)
tZQLAT

Specifies the ZQ calibration latch time in nanoseconds.

(Identifier: MEM_TZQLAT_NS)
tZQCAL

Specifies the ZQ calibration time in nanoseconds.

(Identifier: MEM_TZQCAL_NS)
tMRR

Specifies the Mode Register Read (MRR) command period in nanoseconds.

(Identifier: MEM_TMRR_NS)
tMRR_P

Specifies the Mode Register Read (MRR) pattern to mode register read pattern command spacing in nanoseconds.

(Identifier: MEM_TMRR_P_NS)
tMRW

Specifies the Mode Register Write (MRW) command period in nanoseconds.

(Identifier: MEM_TMRW_NS)
tMRD

Specifies the Mode Register Set (MRS) command delay in nanoseconds.

(Identifier: MEM_TMRD_NS)
tDFE

Specifies the Decision Feedback Equalization (DFE) Mode Register Write update delay time in nanoseconds.

(Identifier: MEM_TDFE_NS)
tDLLK

Specifies the timing of DLLK in nanoseconds.

(Identifier: MEM_TDLLK_NS)
tWTR_S

Specifies the delay from start of internal write transaction to internal read command for different bank group in nanoseconds.

(Identifier: MEM_TWTR_S_NS)
tWTR_L

Specifies the delay from start of internal write transaction to internal read command for same bank group in nanoseconds.

(Identifier: MEM_TWTR_L_NS)
tRTP

Specifies the internal read command to precharge command delay in nanoseconds.

(Identifier: MEM_TRTP_NS)
tPPD

Specifies the Precharge-to-Precharge delay in cycles.

(Identifier: MEM_TPPD_CYC)
tPD

Specifies the minimum power down time in nanoseconds.

(Identifier: MEM_TPD_NS)
tACTPDEN

Specifies the timing of Activate command to power down entry command in cycles.

(Identifier: MEM_TACTPDEN_CYC)
tPRPDEN

Specifies the timing of Precharge All Banks (PREab), Precharge Same Bank (PREsb), or Normal Precharge (PREpb) to power down entry command in cycles.

(Identifier: MEM_TPRPDEN_CYC)
tREFPDEN

Specifies the timing of Refresh All Banks (REFab) or Refresh Same Bank (REFsb) command to power down entry command in cycles.

(Identifier: MEM_TREFPDEN_CYC)
tXP

Specifies the exit power down to next valid command in nanoseconds.

(Identifier: MEM_TXP_NS)
tCPDED

Specifies the command pass disable delay in nanoseconds.

(Identifier: MEM_TCPDED_CYC)
tCSL

Specifies the Self-Refresh CS_n low pulse width in nanoseconds.

(Identifier: MEM_TCSL_NS)
tCKSRX

Specifies the valid clock requirement before SRX in nanoseconds.

(Identifier: MEM_TCKSRX_NS)
tCSH_SREXIT

Specifies the self-refresh exit CS_n high pulse width in nanoseconds.

(Identifier: MEM_TCSH_SREXIT_NS)
tDQSCK_MIN

Specifies the minimum DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in cycles.

(Identifier: MEM_TDQSCK_MIN_CYC)
tDQSCK_MAX

Specifies the maximum DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in cycles.

(Identifier: MEM_TDQSCK_MAX_CYC)
tDQSCK

Specifies the DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in cycles.

(Identifier: MEM_TDQSCK_CYC)
tWPRE_EN

Specifies the write preamble enable window in cycles. The window size depends on the write preamble mode.

(Identifier: MEM_TWPRE_EN_CYC)
tDQSS

Specifies the host and system voltage/temperature drift window of first rising DQS_t preamble edge relative to CAS Write Latency (CWL) CK_t-CK_c edge in cycles.

(Identifier: MEM_TDQSS_CYC)
tCKLCS

Specifies the valid clock requirement after SRE in cycles.

(Identifier: MEM_TCKLCS_CYC)
tWTRA

Specifies the delay from start of internal write transaction to internal read with auto precharge command for same bank in nanoseconds.

(Identifier: MEM_TWTRA_NS)
RDIMM Serial Presence Detect (SPD) Byte 248

Specifies the value of SPD Byte 248 as an integer in decimal.

(Identifier: MEM_SPD248_CK_CONTROL_ENABLE)
RDIMM Serial Presence Detect (SPD) Byte 249

Specifies the value of SPD Byte 249 as an integer in decimal.

(Identifier: MEM_SPD249_QCA_CS_ENABLE)
RDIMM Serial Presence Detect (SPD) Byte 250

Specifies the value of SPD Byte 250 as an integer in decimal.

(Identifier: MEM_SPD250_QCK_SIGNAL_DRIVER_STRENGTH)
RDIMM Serial Presence Detect (SPD) Byte 252

Specifies the value of SPD Byte 252 as an integer in decimal.

(Identifier: MEM_SPD252_QCA_QCS_SIGNAL_DRIVER_STRENGTH)
RDIMM Serial Presence Detect (SPD) Byte 254

Specifies the value of SPD Byte 254 as an integer in decimal.

(Identifier: MEM_SPD254_CK_CA_CS_SLEW_RATE)
tRRD_DLR

Specifies the Activate-to-Activate command delay to different logical ranks in nanoseconds. Only applicable to 3D stacked devices.

(Identifier: MEM_TRRD_DLR_NS)
tFAW_DLR

Specifies the four activate window for different logical ranks in nanoseconds. Only applicable to 3D stacked devices.

(Identifier: MEM_TFAW_DLR_NS)
tCCD_DLR

Specifies the write CAS_n to write CAS_n command delay in different logical ranks, in nanoseconds. Only applicable to 3D stacked devices device.

(Identifier: MEM_TCCD_DLR_NS)
Table 192.  Group: Advanced: Analog Overrides / Overrides / ANALOG_TABLE
Parameter Name Description
Analog Parameter

Name of Analog Parameter to explicitly override; the values will be applied and appear in the list below.

Default value is

Legal values are:

  • Phy AC Drive Strength (PHY_TERM_X_R_S_AC_OUTPUT_OHM)
  • Phy CK Drive Strength (PHY_TERM_X_R_S_CK_OUTPUT_OHM)
  • Phy DQ Drive Strength (PHY_TERM_X_R_S_DQ_OUTPUT_OHM)
  • Phy DQ Slew Rate (PHY_TERM_X_DQ_SLEW_RATE)
  • Phy DQ Input Termination (PHY_TERM_X_R_T_DQ_INPUT_OHM)
  • Phy DQ Initial Vrefin (PHY_TERM_X_DQ_VREF)
  • Phy PLL Reference Clock Input Termination (PHY_TERM_X_R_T_REFCLK_INPUT_OHM)
  • Phy DFE Tap 1 (PHY_DFE_X_TAP_1)
  • Phy DFE Tap 2 (PHY_DFE_X_TAP_2)
  • Phy DFE Tap 3 (PHY_DFE_X_TAP_3)
  • Phy DFE Tap 4 (PHY_DFE_X_TAP_4)
  • Mem Target Write Termination (MEM_ODT_DQ_X_TGT_WR)
  • Mem Non-Target Write Termination (MEM_ODT_DQ_X_NON_TGT_WR)
  • Mem Non-Target Read Termination (MEM_ODT_DQ_X_NON_TGT_RD)
  • Mem DQ Idle Termination (MEM_ODT_DQ_X_IDLE)
  • Mem DQ Drive Strength (MEM_ODT_DQ_X_RON)
  • Mem VrefDQ Value (MEM_VREF_DQ_X_VALUE)
  • Mem CA Termination (MEM_ODT_CA_X_CA)
  • Mem CS Termination (MEM_ODT_CA_X_CS)
  • Mem CK Termination (MEM_ODT_CA_X_CK)
  • Mem VrefCA Value (MEM_VREF_CA_X_CA_VALUE)
  • Mem VrefCS Value (MEM_VREF_CA_X_CS_VALUE)
  • Mem DFE Tap 1 (MEM_DFE_X_TAP_1)
  • Mem DFE Tap 2 (MEM_DFE_X_TAP_2)
  • Mem DFE Tap 3 (MEM_DFE_X_TAP_3)
  • Mem DFE Tap 4 (MEM_DFE_X_TAP_4)
  • Mem RCD CA Input Termination (MEM_RCD_DCA_IBT)
  • Mem RCD CS Input Termination (MEM_RCD_DCS_IBT)
  • Mem RCD CK Input Termination (MEM_RCD_DCK_IBT)
  • Mem RCD Error Input Termination (MEM_RCD_DERROR_IBT)

(Identifier: ANALOG_PARAM_DERIVATION_PARAM_NAME)
Table 193.  Group: Advanced: Analog Overrides / Values
Parameter Name Description
Phy AC Drive Strength

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are:

  • 34 Ohm (with calibration) (SERIES_34_OHM_CAL)
  • 40 Ohm (with calibration) (SERIES_40_OHM_CAL)

(Identifier: PHY_TERM_X_R_S_AC_OUTPUT_OHM)
Phy CK Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the CK Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are:

  • 34 Ohm (with calibration) (SERIES_34_OHM_CAL)
  • 40 Ohm (with calibration) (SERIES_40_OHM_CAL)

(Identifier: PHY_TERM_X_R_S_CK_OUTPUT_OHM)
Phy DQ Drive Strength

This parameter allows you to change the output on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are:

  • 34 Ohm (with calibration) (SERIES_34_OHM_CAL)
  • 40 Ohm (with calibration) (SERIES_40_OHM_CAL)

(Identifier: PHY_TERM_X_R_S_DQ_OUTPUT_OHM)
Phy DQ Slew Rate

Specifies the slew rate of the data bus pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the slew rate that provides the best eye opening for the data bus signals.

Legal values are:

  • Slow (SLOW)
  • Medium (MEDIUM)
  • Fast (FAST)
  • Fastest (FASTEST)

(Identifier: PHY_TERM_X_DQ_SLEW_RATE)
Phy DQ Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are:

  • 40 Ohm (with calibration) (RT_40_OHM_CAL)
  • 50 Ohm (with calibration) (RT_50_OHM_CAL)
  • 60 Ohm (with calibration) (RT_60_OHM_CAL)

(Identifier: PHY_TERM_X_R_T_DQ_INPUT_OHM)
Phy DQ Initial Vrefin

Specifies the initial value for the reference voltage on the data pins(Vrefin). The specified value serves as a starting point and may be overridden by calibration to provide better timing margins.

Legal values are: from 0 to 100

(Identifier: PHY_TERM_X_DQ_VREF)
Phy PLL Reference Clock Input Termination

This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design.

Legal values are:

  • No Termination (RT_OFF)
  • Differential Termination (RT_DIFF)

(Identifier: PHY_TERM_X_R_T_REFCLK_INPUT_OHM)
Phy DFE Tap 1

This parameter allows you to select the amount of bias used on tap 1 of the FPGA DFE.

Legal values are:

  • No Bias (0)
  • -77.00mV (n1)
  • -154.00mV (n2)
  • -231.00mV (n3)
  • -308.00mV (n4)
  • -385.00mV (n5)
  • -462.00mV (n6)
  • -539.00mV (n7)
  • -616.00mV (n8)
  • -693.00mV (n9)
  • -770.00mV (n10)
  • -847.00mV (n11)
  • -924.00mV (n12)
  • -1001.00mV (n13)
  • -1078.00mV (n14)
  • -1155.00mV (n15)
  • -1232.00mV (n16)
  • -1309.00mV (n17)
  • -1386.00mV (n18)
  • -1463.00mV (n19)
  • -1540.00mV (n20)
  • -1617.00mV (n21)
  • -1694.00mV (n22)
  • -1771.00mV (n23)
  • -1848.00mV (n24)
  • -1925.00mV (n25)
  • -2002.00mV (n26)
  • -2079.00mV (n27)
  • -2156.00mV (n28)
  • -2233.00mV (n29)
  • -2310.00mV (n30)
  • -2387.00mV (n31)

(Identifier: PHY_DFE_X_TAP_1)
Phy DFE Tap 2

This parameter allows you to select the amount of bias used on tap 2 of the FPGA DFE.

Legal values are:

  • +269.50mV (p7)
  • +231.00mV (p6)
  • +192.50mV (p5)
  • +154.00mV (p4)
  • +115.50mV (p3)
  • +77.00mV (p2)
  • +38.50mV (p1)
  • No Bias (0)
  • -38.50mV (n1)
  • -77.00mV (n2)
  • -115.50mV (n3)
  • -154.00mV (n4)
  • -192.50mV (n5)
  • -231.00mV (n6)
  • -269.50mV (n7)
  • -308.00mV (n8)

(Identifier: PHY_DFE_X_TAP_2)
Phy DFE Tap 3

This parameter allows you to select the amount of bias used on tap 3 of the FPGA DFE.

Legal values are:

  • +269.50mV (p7)
  • +231.00mV (p6)
  • +192.50mV (p5)
  • +154.00mV (p4)
  • +115.50mV (p3)
  • +77.00mV (p2)
  • +38.50mV (p1)
  • No Bias (0)
  • -38.50mV (n1)
  • -77.00mV (n2)
  • -115.50mV (n3)
  • -154.00mV (n4)
  • -192.50mV (n5)
  • -231.00mV (n6)
  • -269.50mV (n7)
  • -308.00mV (n8)

(Identifier: PHY_DFE_X_TAP_3)
Phy DFE Tap 4

This parameter allows you to select the amount of bias used on tap 4 of the FPGA DFE.

Legal values are:

  • +115.50mV (p3)
  • +77.00mV (p2)
  • +38.50mV (p1)
  • No Bias (0)
  • -38.50mV (n1)
  • -77.00mV (n2)
  • -115.50mV (n3)
  • -154.00mV (n4)

(Identifier: PHY_DFE_X_TAP_4)
Mem Target Write Termination

Specifies the target termination to be used during a write. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are:

  • Disable (off)
  • 240 Ohm (RZQ/1) (1)
  • 120 Ohm (RZQ/2) (2)
  • 80 Ohm (RZQ/3) (3)
  • 60 Ohm (RZQ/4) (4)
  • 48 Ohm (RZQ/5) (5)
  • 40 Ohm (RZQ/6) (6)
  • 34 Ohm (RZQ/7) (7)

(Identifier: MEM_ODT_DQ_X_TGT_WR)
Mem Non-Target Write Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration during a write. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are:

  • Disable (off)
  • 240 Ohm (RZQ/1) (1)
  • 120 Ohm (RZQ/2) (2)
  • 80 Ohm (RZQ/3) (3)
  • 60 Ohm (RZQ/4) (4)
  • 48 Ohm (RZQ/5) (5)
  • 40 Ohm (RZQ/6) (6)
  • 34 Ohm (RZQ/7) (7)

(Identifier: MEM_ODT_DQ_X_NON_TGT_WR)
Mem Non-Target Read Termination

Specifies the termination to be used for the non-target rank in a multi-rank configuration during a read. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are:

  • Disable (off)
  • 240 Ohm (RZQ/1) (1)
  • 120 Ohm (RZQ/2) (2)
  • 80 Ohm (RZQ/3) (3)
  • 60 Ohm (RZQ/4) (4)
  • 48 Ohm (RZQ/5) (5)
  • 40 Ohm (RZQ/6) (6)
  • 34 Ohm (RZQ/7) (7)

(Identifier: MEM_ODT_DQ_X_NON_TGT_RD)
Mem DQ Idle Termination

Specifies the termination to be used for RTT_PARK and DQS_RTT_PARK. For power savings it is recommended to leave this as disabled. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are:

  • Disable (off)
  • 240 Ohm (RZQ/1) (1)
  • 120 Ohm (RZQ/2) (2)
  • 80 Ohm (RZQ/3) (3)
  • 60 Ohm (RZQ/4) (4)
  • 48 Ohm (RZQ/5) (5)
  • 40 Ohm (RZQ/6) (6)
  • 34 Ohm (RZQ/7) (7)

(Identifier: MEM_ODT_DQ_X_IDLE)
Mem DQ Drive Strength

Specifies the termination to be used when driving read data from memory. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X.

Legal values are:

  • 34 Ohm (RZQ/7) (7)
  • 40 Ohm (RZQ/6) (6)
  • 48 Ohm (RZQ/5) (5)

(Identifier: MEM_ODT_DQ_X_RON)
Mem VrefDQ Value

Specifies the initial VrefDQ value to be used.

Legal values are: from 35.00 to 97.50

(Identifier: MEM_VREF_DQ_X_VALUE)
Mem CA Termination

Specifies the termination to be used for the CA bus. This setting only applies to Group B, Group A will always be unterminated. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. "off" means this termination is disabled.

Legal values are:

  • Disable (off)
  • 480 Ohm (RZQ/0.5) (0p5)
  • 240 Ohm (RZQ/1) (1)
  • 120 Ohm (RZQ/2) (2)
  • 80 Ohm (RZQ/3) (3)
  • 60 Ohm (RZQ/4) (4)
  • 40 Ohm (RZQ/6) (6)

(Identifier: MEM_ODT_CA_X_CA)
Mem CS Termination

Specifies the termination to be used for the CS bus. This setting only applies to Group B, Group A will always be unterminated. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. "off" means this termination is disabled.

Legal values are:

  • Disable (off)
  • 480 Ohm (RZQ/0.5) (0p5)
  • 240 Ohm (RZQ/1) (1)
  • 120 Ohm (RZQ/2) (2)
  • 80 Ohm (RZQ/3) (3)
  • 60 Ohm (RZQ/4) (4)
  • 40 Ohm (RZQ/6) (6)

(Identifier: MEM_ODT_CA_X_CS)
Mem CK Termination

Specifies the termination to be used for the CK bus. This setting only applies to Group B, Group A will always be unterminated. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. "off" means this termination is disabled.

Legal values are:

  • Disable (off)
  • 480 Ohm (RZQ/0.5) (0p5)
  • 240 Ohm (RZQ/1) (1)
  • 120 Ohm (RZQ/2) (2)
  • 80 Ohm (RZQ/3) (3)
  • 60 Ohm (RZQ/4) (4)
  • 40 Ohm (RZQ/6) (6)

(Identifier: MEM_ODT_CA_X_CK)
Mem VrefCA Value

Specifies the initial VrefCA value to be used.

Legal values are: from 35.00 to 97.50

(Identifier: MEM_VREF_CA_X_CA_VALUE)
Mem VrefCS Value

Specifies the initial VrefCS value to be used.

Legal values are: from 35.00 to 97.50

(Identifier: MEM_VREF_CA_X_CS_VALUE)
Mem DFE Tap 1

This parameter allows you to select the amount of bias used on tap 1 of the memory DFE.

Legal values are:

  • +50mV (p10)
  • +45mV (p9)
  • +40mV (p8)
  • +35mV (p7)
  • +30mV (p6)
  • +25mV (p5)
  • +20mV (p4)
  • +15mV (p3)
  • +10mV (p2)
  • +5mV (p1)
  • No Bias (0)
  • -5mV (n1)
  • -10mV (n2)
  • -15mV (n3)
  • -20mV (n4)
  • -25mV (n5)
  • -30mV (n6)
  • -35mV (n7)
  • -40mV (n8)
  • -45mV (n9)
  • -50mV (n10)
  • -55mV (n11)
  • -60mV (n12)
  • -65mV (n13)
  • -70mV (n14)
  • -75mV (n15)
  • -80mV (n16)
  • -85mV (n17)
  • -90mV (n18)
  • -95mV (n19)
  • -100mV (n20)
  • -105mV (n21)
  • -110mV (n22)
  • -115mV (n23)
  • -120mV (n24)
  • -125mV (n25)
  • -130mV (n26)
  • -135mV (n27)
  • -140mV (n28)
  • -145mV (n29)
  • -150mV (n30)
  • -155mV (n31)
  • -160mV (n32)
  • -165mV (n33)
  • -170mV (n34)
  • -175mV (n35)
  • -180mV (n36)
  • -185mV (n37)
  • -190mV (n38)
  • -195mV (n39)
  • -200mV (n40)

(Identifier: MEM_DFE_X_TAP_1)
Mem DFE Tap 2

This parameter allows you to select the amount of bias used on tap 2 of the memory DFE.

Legal values are:

  • +75mV (p15)
  • +70mV (p14)
  • +65mV (p13)
  • +60mV (p12)
  • +55mV (p11)
  • +50mV (p10)
  • +45mV (p9)
  • +40mV (p8)
  • +35mV (p7)
  • +30mV (p6)
  • +25mV (p5)
  • +20mV (p4)
  • +15mV (p3)
  • +10mV (p2)
  • +5mV (p1)
  • No Bias (0)
  • -5mV (n1)
  • -10mV (n2)
  • -15mV (n3)
  • -20mV (n4)
  • -25mV (n5)
  • -30mV (n6)
  • -35mV (n7)
  • -40mV (n8)
  • -45mV (n9)
  • -50mV (n10)
  • -55mV (n11)
  • -60mV (n12)
  • -65mV (n13)
  • -70mV (n14)
  • -75mV (n15)

(Identifier: MEM_DFE_X_TAP_2)
Mem DFE Tap 3

This parameter allows you to select the amount of bias used on tap 3 of the memory DFE.

Legal values are:

  • +60mV (p12)
  • +55mV (p11)
  • +50mV (p10)
  • +45mV (p9)
  • +40mV (p8)
  • +35mV (p7)
  • +30mV (p6)
  • +25mV (p5)
  • +20mV (p4)
  • +15mV (p3)
  • +10mV (p2)
  • +5mV (p1)
  • No Bias (0)
  • -5mV (n1)
  • -10mV (n2)
  • -15mV (n3)
  • -20mV (n4)
  • -25mV (n5)
  • -30mV (n6)
  • -35mV (n7)
  • -40mV (n8)
  • -45mV (n9)
  • -50mV (n10)
  • -55mV (n11)
  • -60mV (n12)

(Identifier: MEM_DFE_X_TAP_3)
Mem DFE Tap 4

This parameter allows you to select the amount of bias used on tap 4 of the memory DFE.

Legal values are:

  • +45mV (p9)
  • +40mV (p8)
  • +35mV (p7)
  • +30mV (p6)
  • +25mV (p5)
  • +20mV (p4)
  • +15mV (p3)
  • +10mV (p2)
  • +5mV (p1)
  • No Bias (0)
  • -5mV (n1)
  • -10mV (n2)
  • -15mV (n3)
  • -20mV (n4)
  • -25mV (n5)
  • -30mV (n6)
  • -35mV (n7)
  • -40mV (n8)
  • -45mV (n9)

(Identifier: MEM_DFE_X_TAP_4)
Mem RCD CA Input Termination

This parameter allows you to select the input bus termination of RCD CA input bus. See JEDEC specifications on DDR5RCD04 for the pins covered. The values map to specific termination strengths: 0 -> "60 Ohm", 1 -> "48 Ohm", 3 -> "OFF".

Legal values are:

  • 60 Ohm (0)
  • 48 Ohm (1)
  • Off (3)

(Identifier: MEM_RCD_DCA_IBT)
Mem RCD CS Input Termination

This parameter allows you to select the input bus termination of RCD CS input bus. See JEDEC specifications on DDR5RCD04 for the pins covered. The values map to specific termination strengths: 0 -> "60 Ohm", 1 -> "48 Ohm", 3 -> "OFF".

Legal values are:

  • 60 Ohm (0)
  • 48 Ohm (1)
  • Off (3)

(Identifier: MEM_RCD_DCS_IBT)
Mem RCD CK Input Termination

This parameter allows you to select the input bus termination of CK input bus. See JEDEC specifications on DDR5RCD04 for the pins covered. The values map to specific termination strengths: 0 -> "60 Ohm", 1 -> "48 Ohm", 3 -> "OFF".

Legal values are:

  • 60 Ohm (0)
  • 48 Ohm (1)
  • Off (3)

(Identifier: MEM_RCD_DCK_IBT)
Mem RCD Error Input Termination

This parameter allows you to select the input bus termination of DERROR input bus. See JEDEC specification on DDR5RCD04 for the pins covered. The values map to specific termination strengths: 0 -> "60 Ohm", 1 -> "48 Ohm", 3 -> "OFF".

Legal values are:

  • 60 Ohm (0)
  • 48 Ohm (1)
  • Off (3)

(Identifier: MEM_RCD_DERROR_IBT)
Table 194.  Group: Example Design / Fileset Types
Parameter Name Description
HDL Selection

This option lets you choose the format of HDL in which generated simulation and synthesis files are created. You can select either Verilog or VHDL.

Default value is VERILOG

Legal values are:

  • Verilog (VERILOG)
  • VHDL (VHDL)

(Identifier: EX_DESIGN_HDL_FORMAT)
Generate Synthesis Fileset

Generate Synthesis Example Design.

Default value is true

(Identifier: EX_DESIGN_GEN_SYNTH)
Generate Simulation Fileset

Generate Simulation Example Design.

Default value is true

(Identifier: EX_DESIGN_GEN_SIM)
Table 195.  Group: Example Design / User PLL
Parameter Name Description
Auto-set User PLL Output Clock Frequency

If true, let IP select a reference clock frequency for the user PLL in the example design; if false, let user set a custom value for this parameter.

Default value is true

(Identifier: EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN)
User PLL Output Clock Frequency

Frequency of the core clock in MHz. This clock drives the traffic generator and NoC initiator (If in NoC mode).

Value is specified in megahertz

Default value is 570

(Identifier: EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ)
User PLL Reference Clock Frequency

PLL reference clock frequency in MHz for PLL supplying the core clock.

Value is specified in megahertz

Default value is 100

(Identifier: EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ)
NOC Reference Clock Frequency

Reference Clock Frequency for the NOC control IP.

Value is specified in megahertz

Default value is 100

Legal values are: 25, 100, 125

(Identifier: EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ)
Table 196.  Group: Example Design / Traffic Generator
Parameter Name Description
Traffic Generator Remote Access

Specifies whether the Traffic Generator control and status registers are accessible via JTAG, exported to the fabric, or just disabled.

Default value is JTAG

Legal values are:

  • Exported for Onchip control (EXPORT)
  • Remote through JTAG (JTAG)

(Identifier: EX_DESIGN_TG_CSR_ACCESS_MODE)
Traffic Generator Program

Specifies the traffic pattern to be run.

Default value is MEDIUM

Legal values are:

  • Short Traffic Pattern (SHORT)
  • Medium-length Traffic Pattern (MEDIUM)
  • Long Traffic Pattern (LONG)
  • Infinite Traffic Pattern (INFINITE)

(Identifier: EX_DESIGN_TG_PROGRAM)
Table 197.  Group: Example Design / Performance Monitor
Parameter Name Description
Enable Performance Monitor for Channel 0

If true, example design will include a Performance Monitor instance connected to Channel 0.

Default value is false

(Identifier: EX_DESIGN_PMON_CH0_EN)
Enable Performance Monitor for Channel 1

If true, example design will include a Performance Monitor instance connected to Channel 1.

Default value is false

(Identifier: EX_DESIGN_PMON_CH1_EN)
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