External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
- 4.1.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR4 Component
- 4.3.2. s0_axi4_clock_out for Agilex 7 M-Series External Memory Interfaces (EMIF) IP - DDR5 Component
6.1. Agilex 7 M-Series DDR4 Component External Memory Interfaces (EMIF) IP Parameter Descriptions
Parameter Name | Description |
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Data DQ Width | Number of DQ pins per memory channel, used for data. Default value is 32 Legal values are: 16, 32, 40 (Identifier: MEM_CHANNEL_DATA_DQ_WIDTH) |
ECC DQ Width | Number of additional DQ pins per memory channel, used for out-of-band ECC. If bigger than 0, controller will enable out-of-band ECC. Otherwise, out-of-band ECC will be disabled. Default value is 0 Legal values are: 0, 8 (Identifier: MEM_CHANNEL_ECC_DQ_WIDTH) |
Die DQ Width | Number of DQ pins in each die that makes up the interface. For dual-die packages, this is the width of the die, not the width of full the package. Default value is 16 Legal values are: 8, 16 (Identifier: MEM_DIE_DQ_WIDTH) |
Die Density | Capacity of each memory die (in Gbits), per channel per die. For dual-die packages, this is the density of each die, not the density of the full package. Default value is 8 Legal values are:
(Identifier: MEM_DIE_DENSITY_GBITS) |
CS Width | Specifies the total number of CS pins used by each channel. Default value is 1 Legal values are: 1, 2 (Identifier: MEM_CHANNEL_CS_WIDTH) |
Memory Speedbin | Specifies the speedbin of the memory device(s) of which the interface consists. Default value is 3200W Legal values are:
(Identifier: MEM_SPEEDBIN) |
Use AC Mirroring | Enable command-address mirroring for multi-rank DDR4 interfaces per JEDEC Standard. Default value is false (Identifier: MEM_AC_MIRRORING_EN) |
Share CK Pins Between Ranks | Specifies whether all the ranks in the same channel should share one pair of memory interface differential clock. Default value is false (Identifier: MEM_RANKS_SHARE_CK_EN) |
Use AC Parity | Specifies whether address-command parity is enabled. If enabled then command latency is increased by the value of parameter "Address-Command Latency Mode". Default value is false (Identifier: MEM_AC_PARITY_EN) |
Auto-set Memory Operating Frequency | If true, let IP select max frequency that this configuration can support for the current device speedgrade. If false, user can set custom value for operating frequency. Default value is true (Identifier: MEM_OPERATING_FREQ_MHZ_AUTOSET_EN) |
Memory Operating Frequency | Specifies the frequency at which the memory interface will run. Value is specified in megahertz Legal values are: 666.667, 800, 933.333, 1066.667, 1200, 1333.333, 1466.667, 1600 (Identifier: MEM_OPERATING_FREQ_MHZ) |
Parameter Name | Description |
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Auto-set PLL Reference Clock Frequency | If true, let IP select max PLL refclk frequency that this configuration can support. If false, user can set custom value for PLL refclk frequency. Default value is true (Identifier: PHY_REFCLK_FREQ_MHZ_AUTOSET_EN) |
Enable Advanced List of PLL Reference Clock Frequencies | If true, provide extended list of possible refclk values. Otherwise, prune possible list of refclk values to a more reasonable length. Default value is false (Identifier: PHY_REFCLK_ADVANCED_SELECT_EN) |
Reference Clock Frequency | Specifies the reference clock frequency for the EMIF IOPLL. Value is specified in megahertz (Identifier: PHY_REFCLK_FREQ_MHZ) |
AC Placement | Indicates location on the device where the interface will reside (specifically, the location of the AC lanes in terms I/O BANK and TOP vs BOT part of the I/O BANK). Legal ranges are derived from device floorplan. Default value is BOT Legal values are:
(Identifier: PHY_AC_PLACEMENT) |
Alert_n AC-Lane Index | Specifies the AC lane index in which to place the ALERT_N pin. Default value is AC2 Legal values are: AC2, AC3 (Identifier: PHY_ALERT_N_PLACEMENT) |
Force Using 4 AC Lanes | Specifies if the minimum number of AC lanes for the memory interface should be forced to 4. Default value is false (Identifier: PHY_FORCE_MIN_4_AC_LANES_EN) |
Auto-set Mainband Access Mode | If true, let IP select most likely usecase for the PHY_MAINBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode. Default value is true (Identifier: PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN) |
Mainband Access Mode | Specifies the path through which the EMIF QHIP mainband interface is exposed to the user. The mainband interface is the AXI4 interface to the memory controller. Legal values are:
(Identifier: PHY_MAINBAND_ACCESS_MODE) |
Auto-set Sideband Access Mode | If true, let IP select most likely usecase for the PHY_SIDEBAND_ACCESS_MODE; if false, let user set a custom value for sideband access mode. Default value is true (Identifier: PHY_SIDEBAND_ACCESS_MODE_AUTOSET_EN) |
Sideband Access Mode | Specifies the path through which the EMIF QHIP sideband interface is exposed to the user. The sideband interface is the AXI4-Lite interface to the IOSSM. Legal values are:
(Identifier: PHY_SIDEBAND_ACCESS_MODE) |
Pin Swizzle Map | Specifies the swizzle map for the data lanes and pins. (Identifier: PHY_SWIZZLE_MAP) |
Use Debug Toolkit | If enabled, the AXI-L port will be connected to SLD nodes, allowing for a system-console avalon manager interface to interact with this AXI-L subordinate interface. Default value is false (Identifier: DEBUG_TOOLS_EN) |
Instance ID | Instance ID of the EMIF IP. This is useful when using a discovery mechanism over the side-band interface, to identify which EMIF instance's mailbox is at which offset. If expecting to use a discovery mechanism in hardware, this parameter must be set uniquely for all EMIFs that share a sideband. Otherwise, this parameter can be ignored / kept at the default value. Default value is 0 Legal values are: from 0 to 6 (Identifier: INSTANCE_ID) |
Parameter Name | Description |
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Use ECC Autocorrection | If ECC is enabled, specifies whether single-bit-errors (SBEs) should be corrected or just reported. Default value is true (Identifier: CTRL_ECC_AUTOCORRECT_EN) |
Use Data Masking | Specifies whether Data Masking is enabled by the controller. When ECC is enabled, RMWs will occur (to recompute / write ECC), regardless of whether this is enabled. Default value is false (Identifier: CTRL_DM_EN) |
Use WDBI | Specifies whether write Data-bus-inversion is enabled by the controller. Default value is false (Identifier: CTRL_WR_DBI_EN) |
Use RDBI | Specifies whether read Data-bus-inversion is enabled by the controller. Default value is false (Identifier: CTRL_RD_DBI_EN) |
Controller Performance Profile | Group of Controller settings to optimize performance based on expected traffic patterns. Choose "Custom" for fine-granular control Default value is SEQ Legal values are:
(Identifier: CTRL_PERFORMANCE_PROFILE) |
Force Auto-Precharge | Controller will terminate all transactions with an auto-precharge when enabled. For per-transaction granularity, leave this option disabled and use the AxUSER control signals instead. Default value is false (Identifier: CTRL_AUTO_PRECHARGE_EN) |
Bank Group Rotation | Moves a number of Bank Group pins lower in the address order Default value is 1 Legal values are:
(Identifier: CTRL_BG_ROTATE_EN) |
Enable Row/CS Swap | Specifies whether the highest order address bits are the CS bit (false) or Row bits (true) Default value is false (Identifier: DIAG_HMC_ADDR_SWAP_EN) |
Parameter Name | Description |
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Additional read-to-write turnaround time (same rank) | Additional memory clock cycles of delay between read and write operations within the same rank Value is specified in Cycles Default value is 0 Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 (Identifier: TURNAROUND_R2W_SAMECS_CYC) |
Additional read-to-read turnaround time (same rank) | Additional memory clock cycles of delay between read operations within the same rank Value is specified in Cycles Default value is 0 Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 (Identifier: TURNAROUND_R2R_SAMECS_CYC) |
Additional write-to-write turnaround time (same rank) | Additional memory clock cycles of delay between write operations within the same rank Value is specified in Cycles Default value is 0 Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 (Identifier: TURNAROUND_W2W_SAMECS_CYC) |
Additional write-to-read turnaround time (same rank) | Additional memory clock cycles of delay between read and write operations within the same rank Value is specified in Cycles Default value is 0 Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 (Identifier: TURNAROUND_W2R_SAMECS_CYC) |
Additional read-to-write turnaround time (different ranks) | Additional controller cycles of delay between read and write operations across different ranks Value is specified in Cycles Default value is 0 Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 (Identifier: TURNAROUND_R2W_DIFFCS_CYC) |
Additional read-to-read turnaround time (different ranks) | Additional controller cycles of delay between read operations across different ranks Value is specified in Cycles Default value is 0 Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 (Identifier: TURNAROUND_R2R_DIFFCS_CYC) |
Additional write-to-write turnaround time (different ranks) | Additional controller cycles of delay between write operations across different ranks Value is specified in Cycles Default value is 0 Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 (Identifier: TURNAROUND_W2W_DIFFCS_CYC) |
Additional write-to-read turnaround time (different ranks) | Additional controller cycles of delay between write and read operations across different ranks Value is specified in Cycles Default value is 0 Legal values are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 (Identifier: TURNAROUND_W2R_DIFFCS_CYC) |
Parameter Name | Description |
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Enable Margining during Calibration | Enable margining stages of calibration for use with the EMIF Debug Toolkit. This will increase calibration time Default value is false (Identifier: ADV_CAL_ENABLE_MARGIN) |
Enable REQ Calibration | Enable the Read DQ Equalization stage as part of calibration. This will increase calibration time but will also improve top-line performance Default value is false (Identifier: ADV_CAL_ENABLE_REQ) |
Enable WEQ Calibration | Run the Write DQ Equalization stage as part of calibration. This will increase calibration time but will also improve top-line performance Default value is false (Identifier: ADV_CAL_ENABLE_WEQ) |
Parameter Name | Description |
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JEDEC Parameter | Name of JEDEC Parameter to explicitly override; the values will be applied and appear in the list below. Default value is Legal values are:
(Identifier: JEDEC_OVERRIDE_TABLE_PARAM_NAME) |
Parameter Name | Description |
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Write Preamble Length | Specifies the write preamble length in cycles. (Identifier: MEM_WR_PREAMBLE_MODE) |
Read Preamble Length | Specifies the read preamble length in cycles. (Identifier: MEM_RD_PREAMBLE_MODE) |
Read Latency | Read Latency of the memory device in clock cycles. (Identifier: MEM_CL_CYC) |
Write Latency | Write Latency in clock cycles. (Identifier: MEM_CWL_CYC) |
tREFI | Specifies the average refresh interval in nanoseconds. (Identifier: MEM_TREFI_NS) |
tRAS | Specifies the activation-to-precharge command period in nanoseconds. (Identifier: MEM_TRAS_NS) |
tRCD | Specifies the activation to interval read or write delay interval in nanoseconds. (Identifier: MEM_TRCD_NS) |
tRP | Specifies the precharge command period in nanoseconds. (Identifier: MEM_TRP_NS) |
tRC | Specifies the activate-to-activate or activate-to-refresh command period in nanoseconds. (Identifier: MEM_TRC_NS) |
tCCD_L | Specifies the CAS-to-CAS command delay for the same bank group in nanoseconds. (Identifier: MEM_TCCD_L_NS) |
tCCD_S | Specifies the CAS-to-CAS command delay for different bank groups in nanoseconds. (Identifier: MEM_TCCD_S_NS) |
tRRD_L | Specifies the activation-to-activation command delay for the same bank group in nanoseconds. (Identifier: MEM_TRRD_L_NS) |
tRRD_S | Specifies the activation-to-activation command delay for different bank groups in nanoseconds. (Identifier: MEM_TRRD_S_NS) |
tFAW | Specifies the four-activate-window in nanoseconds. (Identifier: MEM_TFAW_NS) |
tWTR_L | Specifies the minimum delay from the start of an internal write transaction to the immediately next internal read command for the same bank group in nanoseconds. (Identifier: MEM_TWTR_L_NS) |
tWTR_S | Specifies the minimum delay from the start of an internal write transaction to the immediately next internal read command for different bank groups in nanoseconds. (Identifier: MEM_TWTR_S_NS) |
tWR | Specifies the write recovery time in nanoseconds. (Identifier: MEM_TWR_NS) |
tMRD | Specifies the mode-register command cycle time in nanoseconds. (Identifier: MEM_TMRD_NS) |
tCKSRE | Specifies the amount of time, in nanoseconds, required after self-refresh entry or power-down entry. (Identifier: MEM_TCKSRE_NS) |
tCKSRX | Specifies the amount of time, in nanoseconds, required before self-refresh exit, power-down exit, or reset exit. (Identifier: MEM_TCKSRX_NS) |
tCKE | Specifies the minimum CKE low pulse width from self-refresh entry to self-refresh exit in nanoseconds. (Identifier: MEM_TCKE_NS) |
tCKESR | Specifies the minimum CKE low pulse width from self-refresh entry to self-refresh exit in memory clock cycles. (Identifier: MEM_TCKESR_CYC) |
tMPRR | Specifies the multi-purpose register recovery time measured in nanoseconds. (Identifier: MEM_TMPRR_NS) |
tRFC | Specifies the refresh-to-activate or refresh-to-refresh command period in nanoseconds. (Identifier: MEM_TRFC_NS) |
tDQSCK | Specifies the minimum DQS_t, DQS_c rising edge output timing location from rising CK_t, CK_c in nanoseconds. (Identifier: MEM_TDQSCK_NS) |
tRFC_DLR | Specifies the refresh cycle time across different logical rank in nanoseconds. Only applicable to 3DS devices. (Identifier: MEM_TRFC_DLR_NS) |
tRRD_DLR | Specifies the activation-to-activation time across different logical rank in nanoseconds. Only applicable to 3DS devices. (Identifier: MEM_TRRD_DLR_NS) |
tFAW_DLR | Specifies the four-activate-window across different logical ranks in nanoseconds. (Identifier: MEM_TFAW_DLR_NS) |
tCCD_DLR | Specifies the CAS-to-CAS delay across different logical ranks in nanoseconds. (Identifier: MEM_TCCD_DLR_NS) |
tXP | Specifies the delay from power down exit with DLL on to any valid command, or from precharge power down with with DLL frozen to commands not requiring a locked DLL. Measured in nanoseconds. (Identifier: MEM_TXP_NS) |
tXS | Specifies the delay from self refresh exit to commands not requiring a locked DLL in nanoseconds. (Identifier: MEM_TXS_NS) |
tXSDLL | Specifies the delay from self refresh exit to commands requiring a locked DLL in nanoseconds. (Identifier: MEM_TXS_DLL_NS) |
tCPDED | Specifies the command pass disable delay measured in nanoseconds. (Identifier: MEM_TCPDED_NS) |
tMOD | Specifies the mode register set command update delay in nanoseconds. (Identifier: MEM_TMOD_NS) |
tZQCS | Specifies the normal operation short calibration time in nanoseconds. (Identifier: MEM_TZQCS_NS) |
tZQINIT | Specifies the power-up and reset calibration time in cycles. (Identifier: MEM_TZQINIT_CYC) |
tZQOPER | Specifies the normal operation full calibration time in cycles. (Identifier: MEM_TZQOPER_CYC) |
Parameter Name | Description |
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Analog Parameter | Name of Analog Parameter to explicitly override; the values will be applied and appear in the list below. Default value is Legal values are:
(Identifier: ANALOG_PARAM_DERIVATION_PARAM_NAME) |
Parameter Name | Description |
---|---|
Phy AC Drive Strength | This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design. Legal values are:
(Identifier: PHY_TERM_X_R_S_AC_OUTPUT_OHM) |
Phy CK Drive Strength | This parameter allows you to change the output on chip termination settings for the selected I/O standard on the CK Pins. Perform board simulation with IBIS models to determine the best settings for your design. Legal values are:
(Identifier: PHY_TERM_X_R_S_CK_OUTPUT_OHM) |
Phy DQ Drive Strength | This parameter allows you to change the output on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design. Legal values are:
(Identifier: PHY_TERM_X_R_S_DQ_OUTPUT_OHM) |
Phy DQ Slew Rate | Specifies the slew rate of the data bus pins. The slew rate (or edge rate) describes how quickly the signal can transition, measured in voltage per unit time. Perform board simulations to determine the slew rate that provides the best eye opening for the data bus signals. Legal values are:
(Identifier: PHY_TERM_X_DQ_SLEW_RATE) |
Phy DQ Input Termination | This parameter allows you to change the input on chip termination settings for the selected I/O standard on the DQ Pins. Perform board simulation with IBIS models to determine the best settings for your design. Legal values are:
(Identifier: PHY_TERM_X_R_T_DQ_INPUT_OHM) |
Phy DQ Initial Vrefin | Specifies the initial value for the reference voltage on the data pins(Vrefin). The specified value serves as a starting point and may be overridden by calibration to provide better timing margins. Legal values are: from 0 to 100 (Identifier: PHY_TERM_X_DQ_VREF) |
Phy PLL Reference Clock Input Termination | This parameter allows you to change the input on chip termination settings for the selected I/O standard on the refclk input pins. Perform board simulation with IBIS models to determine the best settings for your design. Legal values are:
(Identifier: PHY_TERM_X_R_T_REFCLK_INPUT_OHM) |
Mem Target Write Termination | Specifies the target termination to be used during a write. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. Legal values are:
(Identifier: MEM_ODT_DQ_X_TGT_WR) |
Mem Non-Target Write Termination | Specifies the termination to be used for the non-target rank in a multi-rank configuration during a write. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. Legal values are:
(Identifier: MEM_ODT_DQ_X_NON_TGT_WR) |
Mem Non-Target Read Termination | Specifies the termination to be used for the non-target rank in a multi-rank configuration during a read. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. Legal values are:
(Identifier: MEM_ODT_DQ_X_NON_TGT_RD) |
Mem DQ Drive Strength | Specifies the termination to be used when driving read data from memory. The value of this parameter represents X, where: termination = RZQ/X = (240 Ohm)/X. Legal values are:
(Identifier: MEM_ODT_DQ_X_RON) |
Mem VrefDQ Range | Specifies which of the memory protocol defined ranges will be used. Legal values are:
(Identifier: MEM_VREF_DQ_X_RANGE) |
Mem VrefDQ Value | Specifies the initial VrefDQ value to be used. Legal values are: from 60.00 to 92.50, from 45.00 to 75.00 (Identifier: MEM_VREF_DQ_X_VALUE) |
Parameter Name | Description |
---|---|
HDL Selection | This option lets you choose the format of HDL in which generated simulation and synthesis files are created. You can select either Verilog or VHDL. Default value is VERILOG Legal values are:
(Identifier: EX_DESIGN_HDL_FORMAT) |
Generate Synthesis Fileset | Generate Synthesis Example Design. Default value is true (Identifier: EX_DESIGN_GEN_SYNTH) |
Generate Simulation Fileset | Generate Simulation Example Design. Default value is true (Identifier: EX_DESIGN_GEN_SIM) |
Parameter Name | Description |
---|---|
Auto-set User PLL Output Clock Frequency | If true, let IP select a reference clock frequency for the user PLL in the example design; if false, let user set a custom value for this parameter. Default value is true (Identifier: EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN) |
User PLL Output Clock Frequency | Frequency of the core clock in MHz. This clock drives the traffic generator and NoC initiator (If in NoC mode). Value is specified in megahertz Default value is 570 (Identifier: EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ) |
User PLL Reference Clock Frequency | PLL reference clock frequency in MHz for PLL supplying the core clock. Value is specified in megahertz Default value is 100 (Identifier: EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ) |
NOC Reference Clock Frequency | Reference Clock Frequency for the NOC control IP. Value is specified in megahertz Default value is 100 Legal values are: 25, 100, 125 (Identifier: EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ) |
Parameter Name | Description |
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Traffic Generator Remote Access | Specifies whether the Traffic Generator control and status registers are accessible via JTAG, exported to the fabric, or just disabled. Default value is JTAG Legal values are:
(Identifier: EX_DESIGN_TG_CSR_ACCESS_MODE) |
Traffic Generator Program | Specifies the traffic pattern to be run. Default value is MEDIUM Legal values are:
(Identifier: EX_DESIGN_TG_PROGRAM) |
Parameter Name | Description |
---|---|
Enable Performance Monitor for Channel 0 | If true, example design will include a Performance Monitor instance connected to Channel 0. Default value is false (Identifier: EX_DESIGN_PMON_CH0_EN) |