External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

ID 772538
Date 11/18/2024
Public

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4.5.3. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR5

Reset for mainband, from primary I/O bank, indicating the calibration is complete. Only available if mainband is accessed through fabric.

Table 83.  Interface: s0_axi4_ctrl_readyInterface type: reset
Port Name Direction Description
s0_axi4_reset_n Output Output signal from EMIF IP (primary I/O bank), indicating that Calibration of the channels in this I/O bank is complete, and controllers in this I/O bank are ready for use.