External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

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ID 772538
Date 11/18/2024
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Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP 2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction 3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture 4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals 5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP 6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support 7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support 8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support 9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure 10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization 11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging 12. Agilex™ 7 FPGA EMIF IP - Mailbox Support 13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP x
1.1. Release Information
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction x
2.1. Agilex™ 7 M-Series EMIF IP Protocol and Feature Support 2.2. Agilex™ 7 M-Series EMIF IP Design Flow 2.3. Agilex™ 7 M-Series EMIF IP Design Checklist
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture x
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction 3.2. Agilex™ 7 M-Series EMIF Sequencer 3.3. Agilex™ 7 M-Series EMIF Controller 3.4. Agilex™ 7 M-Series EMIF IP for Hard Processor Subsystem (HPS)
3.1. Agilex™ 7 M-Series EMIF Architecture: Introduction x
3.1.1. Agilex™ 7 M-Series EMIF Architecture: I/O Subsystem 3.1.2. Agilex™ 7 M-Series EMIF Architecture: I/O SSM 3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank 3.1.4. Agilex™ 7 M-Series EMIF Architecture: I/O Lane 3.1.5. Agilex™ 7 M-Series EMIF Architecture: Input DQS Clock Tree 3.1.6. Agilex™ 7 M-Series EMIF Architecture: PHY Clock Tree 3.1.7. Agilex™ 7 M-Series EMIF Architecture: PLL Reference Clock Networks 3.1.8. Agilex™ 7 M-Series EMIF Architecture: Clock Phase Alignment 3.1.9. User Clock in Different Core Access Modes
3.1.3. Agilex™ 7 M-Series EMIF Architecture: I/O Bank x
3.1.3.1. Lockstep Configuration 3.1.3.2. DDR4 Pin Placement 3.1.3.3. DDR5 Pin Placement 3.1.3.4. LPDDR5 Pin Placement 3.1.3.5. I/O Sub-Bank Usage
3.3. Agilex™ 7 M-Series EMIF Controller x
3.3.1. Hard Memory Controller
3.3.1. Hard Memory Controller x
3.3.1.1. Hard Memory Controller Features
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals x
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component 4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component 4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5
4.1. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 Component x
4.1.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 Component 4.1.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 Component
4.2. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR4 DIMM x
4.2.1. s0_axi4_clock_out for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.10. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR4 DIMM 4.2.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR4 DIMM
4.3. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 Component x
4.3.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.2. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.3. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.4. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.5. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.6. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.7. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.8. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.9. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.10. mem_reset_n_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.11. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 Component 4.3.12. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 Component
4.4. IP Interfaces for External Memory Interfaces (EMIF) IP - DDR5 DIMM x
4.4.1. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.2. s1_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.3. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.4. core_init_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.5. s0_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.6. s1_axi4 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.7. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.8. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.9. s0_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.10. s1_axi4lite_clock for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.11. s1_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.12. s1_axi4lite for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.13. mem_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.14. mem_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.15. mem_reset_n for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.16. mem_ck_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.17. mem_ck_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.18. mem_i3c for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.19. oct_0 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.20. oct_1 for External Memory Interfaces (EMIF) IP - DDR5 DIMM 4.4.21. ref_clk for External Memory Interfaces (EMIF) IP - DDR5 DIMM
4.5. IP Interfaces for External Memory Interfaces (EMIF) IP - LPDDR5 x
4.5.1. s0_axi4_clock_in for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.2. core_init_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.3. s0_axi4_ctrl_ready for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.4. s0_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.5. s1_axi4 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.6. s0_axi4lite_clock for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.7. s0_axi4lite_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.8. s0_axi4lite for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.9. mem_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.10. mem_ck_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.11. mem_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.12. mem_ck_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.13. mem_reset_n for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.14. oct_0 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.15. oct_1 for External Memory Interfaces (EMIF) IP - LPDDR5 4.5.16. ref_clk for External Memory Interfaces (EMIF) IP - LPDDR5
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP x
5.1. Simulation Walkthrough
5.1. Simulation Walkthrough x
5.1.1. Calibration 5.1.2. Simulation Scripts 5.1.3. Functional Simulation with Verilog HDL 5.1.4. Simulating the Design Example
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support x
6.1. External Memory Interfaces (EMIF) IP - DDR4 Component Parameter Descriptions 6.2. External Memory Interfaces (EMIF) IP - DDR4 DIMM Parameter Descriptions 6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 6.4. DDR4 Board Design Guidelines
6.3. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 6.3.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP
6.3.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
6.3.1.1. Estimating Pin Requirements 6.3.1.2. DIMM Options 6.3.1.3. Maximum Number of Interfaces
6.3.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
6.3.2.1. OCT 6.3.2.2. PLL
6.3.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR4 EMIF IP x
6.3.4.1. Address and Command Pin Placement for DDR4 6.3.4.2. DDR4 Data Width Mapping 6.3.4.3. General Guidelines - DDR4 6.3.4.4. x4 DIMM Implementation 6.3.4.5. Specific Pin Connection Requirements 6.3.4.6. Command and Address Signals 6.3.4.7. Clock Signals 6.3.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.4. DDR4 Board Design Guidelines x
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices 6.4.2. General Layout Routing Guidelines 6.4.3. Reference Stackup 6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies 6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies
6.4.1. Terminations for DDR4 with Agilex™ 7 M-Series Devices x
6.4.1.1. Dynamic On-Chip Termination (OCT) 6.4.1.2. Dynamic On-Die Termination (ODT) in DDR4 6.4.1.3. Choosing Terminations on Agilex™ 7 M-Series FPGA Devices 6.4.1.4. On-Chip Termination Recommendations for Agilex™ 7 M-Series FPGA Devices
6.4.4. Agilex™ 7 M-Series EMIF-Specific Routing Guidelines for Various DDR4 Topologies x
6.4.4.1. One DIMM per Channel (1DPC) for UDIMM, RDIMM, and SODIMM DDR4 Topologies 6.4.4.2. Skew Matching Guidelines for DIMM Configurations 6.4.4.3. Power Delivery Recommendations for the Memory / DIMM Side
6.4.5. DDR4 Routing Guidelines: Discrete (Component) Topologies x
6.4.5.1. Single Rank and Dual Rank x 8 Discrete (Component) Topology 6.4.5.2. Single Rank x16 and Dual Rank x16 Discrete (Component) Topology 6.4.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies 6.4.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations 6.4.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations 6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
6.4.5.6. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
6.4.5.6.1. DDR4 Byte Lane Swapping 6.4.5.6.2. DDR4 Address and Command and CLK Lane 6.4.5.6.3. DDR4 Interface x8 Data Lane 6.4.5.6.4. DDR4 Interface x4 Data Lane 6.4.5.6.5. Pin Swizzling
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support x
7.1. External Memory Interfaces (EMIF) IP - DDR5 Component Parameter Descriptions 7.2. External Memory Interfaces (EMIF) IP - DDR5 DIMM Parameter Descriptions 7.3. PHY DFE Tap Bias Values for DDR5 7.4. MEM DFE Tap Bias Values for DDR5 7.5. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 7.6. DDR5 Board Design Guidelines
7.5. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
7.5.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 7.5.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 7.5.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 7.5.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP 7.5.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines
7.5.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
7.5.1.1. Estimating Pin Requirements 7.5.1.2. DIMM Options 7.5.1.3. Maximum Number of Interfaces
7.5.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
7.5.2.1. OCT 7.5.2.2. PLL
7.5.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
7.5.3.1. General Guidelines - DDR5 7.5.3.2. x4 DIMM Implementation 7.5.3.3. Specific Pin Connection Requirements 7.5.3.4. Command and Address Signals 7.5.3.5. Clock Signals 7.5.3.6. Data, Data Strobes, DM, and Optional ECC Signals
7.5.4. Pin Placements for Agilex™ 7 M-Series FPGA DDR5 EMIF IP x
7.5.4.1. Address and Command Pin Placement for DDR5 7.5.4.2. DDR5 Data Width Mapping
7.5.5. Agilex™ 7 M-Series EMIF Pin Swapping Guidelines x
7.5.5.1. DDR5 Byte Lane Swapping 7.5.5.2. DDR5 Address and Command and CLK Lane 7.5.5.3. DDR5 Interface x8 Data Lane 7.5.5.4. DDR5 Interface x4 Data Lane 7.5.5.5. Pin Swizzling
7.6. DDR5 Board Design Guidelines x
7.6.1. PCB Stack-up and Design Considerations 7.6.2. General Design Considerations 7.6.3. DDR Differential Signals Routing 7.6.4. Ground Plane and Return Path 7.6.5. RDIMM, UDIMM, and SODIMM Break-in Layout Guidelines 7.6.6. DRAM Break-in Layout Guidelines 7.6.7. General Notes for EMIF Routing Guidelines Tables 7.6.8. DDR5 PCB Layout Guidelines 7.6.9. DDR5 RDIMM Power Management IC 7.6.10. DDR5 Simulation Strategy
7.6.8. DDR5 PCB Layout Guidelines x
7.6.8.1. DDR5 Discrete Component/Memory Down Topology: Single Rank x8 or x16, Dual Rank x8 or x16 7.6.8.2. Routing Guidelines for DDR5 Memory Down: Single Rank or Dual Rank (x8 bit or x16 bit) Configurations 7.6.8.3. Routing Guidelines for DDR5 RDIMM, UDIMM, and SODIMM Configurations 7.6.8.4. Example of a DDR5 layout on an Altera FPGA Platform Board
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support x
8.1. External Memory Interfaces (EMIF) IP - LPDDR5 Parameter Descriptions 8.2. PHY DFE Tap Bias Values for LPDDR5 8.3. MEM DFE Tap Bias Values for LPDDR5 8.4. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning 8.5. LPDDR5 Board Design Guidelines
8.4. Agilex™ 7 M-Series FPGA EMIF IP Pin and Resource Planning x
8.4.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins 8.4.2. Agilex™ 7 M-Series FPGA EMIF IP Resources 8.4.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP 8.4.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP
8.4.1. Agilex™ 7 M-Series FPGA EMIF IP Interface Pins x
8.4.1.1. Estimating Pin Requirements 8.4.1.2. LPDDR5 Component Options 8.4.1.3. Maximum Number of Interfaces
8.4.2. Agilex™ 7 M-Series FPGA EMIF IP Resources x
8.4.2.1. OCT 8.4.2.2. PLL
8.4.3. Pin Guidelines for Agilex™ 7 M-Series FPGA EMIF IP x
8.4.3.1. General Guidelines - LPDDR5 8.4.3.2. Specific Pin Connection Requirements 8.4.3.3. Command and Address Signals 8.4.3.4. Clock Signals
8.4.4. Pin Placements for Agilex™ 7 M-Series FPGA LPDDR5 EMIF IP x
8.4.4.1. Address and Command Pin Placement for LPDDR5 8.4.4.2. LPDDR5 Data Width Mapping 8.4.4.3. LPDDR5 Byte Lane Swapping
8.5. LPDDR5 Board Design Guidelines x
8.5.1. PCB Stack-up and Design Considerations 8.5.2. General Design Considerations 8.5.3. DDR Differential Signals Routing 8.5.4. Ground Plane and Return Path 8.5.5. DRAM Break-in Layout Guidelines 8.5.6. General Notes for EMIF Routing Guidelines Tables 8.5.7. LPDDR5 PCB Layout Guidelines 8.5.8. LPDDR5 Simulation Strategy
8.5.7. LPDDR5 PCB Layout Guidelines x
8.5.7.1. LPDDR5 Discrete Component/Memory Down Topology, Single Rank or Dual Rank 8.5.7.2. Routing Guidelines for LPDDR5 Memory Down Topology 8.5.7.3. Example of an LPDDR5 Layout on an Altera® FPGA Platform Board
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure x
9.1. Timing Closure 9.2. Optimizing Timing
9.1. Timing Closure x
9.1.1. Timing Analysis
9.1.1. Timing Analysis x
9.1.1.1. PHY or Core
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization x
10.1. Interface Standard 10.2. Bank Management Efficiency 10.3. Data Transfer 10.4. Improving Controller Efficiency
10.4. Improving Controller Efficiency x
10.4.1. Frequency of Operation 10.4.2. Series of Reads or Writes 10.4.3. AXI to Memory Mapping
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging x
11.1. Interface Configuration Performance Issues 11.2. Functional Issue Evaluation 11.3. Timing Issue Characteristics 11.4. Verifying Memory IP Using the Signal Tap Logic Analyzer 11.5. Debugging with the External Memory Interface Debug Toolkit 11.6. Generating Traffic with the Test Engine IP 11.7. Guidelines for Developing HDL for Traffic Generator 11.8. Guidelines for Traffic Generator Status Check
11.1. Interface Configuration Performance Issues x
11.1.1. Interface Configuration Bottleneck and Efficiency Issues
11.2. Functional Issue Evaluation x
11.2.1. Altera IP Memory Model 11.2.2. Vendor Memory Model 11.2.3. Transcript Window Messages
11.3. Timing Issue Characteristics x
11.3.1. Evaluating FPGA Timing Issues 11.3.2. Evaluating External Memory Interface Timing Issues
11.5. Debugging with the External Memory Interface Debug Toolkit x
11.5.1. Prerequisites for Using the EMIF Debug Toolkit 11.5.2. Configuring Your Design to Use the EMIF Debug Toolkit 11.5.3. Launching the EMIF Debug Toolkit 11.5.4. Using the EMIF Debug Toolkit
11.5.4. Using the EMIF Debug Toolkit x
11.5.4.1. Rerunning Calibration 11.5.4.2. Rerunning the Test Engine 11.5.4.3. Saving Debug Print 11.5.4.4. Calibration Reports 11.5.4.5. Driver Margining Tab 11.5.4.6. Pin Delay Settings Tab
11.8. Guidelines for Traffic Generator Status Check x
11.8.1. Status Check Using the Signal Tap Logic Analyzer 11.8.2. Exporting the Status Interface to the Top-Level Design
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support x
12.1. Agilex™ 7 Mailbox Structure and Register Definitions 12.2. Sending a Mailbox Command
12.1. Agilex™ 7 Mailbox Structure and Register Definitions x
12.1.1. Mailbox Supported Commands 12.1.2. Mailbox Command Definitions 12.1.3. ECC Syndrome Codes
12.2. Sending a Mailbox Command x
12.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Using Mailbox 12.2.2. Example 2: Reading the Memory Clock Frequency for an Interface 12.2.3. Example 3: Sending Recalibration Request and Reading Calibration Status Using the Mailbox
1. About the External Memory Interfaces Agilex™ 7 M-Series FPGA IP
2. Agilex™ 7 M-Series FPGA EMIF IP – Introduction
3. Agilex™ 7 M-Series FPGA EMIF IP – Product Architecture
4. Agilex™ 7 M-Series FPGA EMIF IP – End-User Signals
5. Agilex™ 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Agilex™ 7 M-Series FPGA EMIF IP – DDR4 Support
7. Agilex™ 7 M-Series FPGA EMIF IP – DDR5 Support
8. Agilex™ 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Agilex™ 7 M-Series FPGA EMIF IP – Timing Closure
10. Agilex™ 7 M-Series FPGA EMIF IP – Controller Optimization
11. Agilex™ 7 M-Series FPGA EMIF IP – Debugging
12. Agilex™ 7 FPGA EMIF IP - Mailbox Support
13. Document Revision History for External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide

12.2.1. Example 1: Reading IP_TYPE and IP_INSTANCE_ID of All the Interfaces in the IO96B Using Mailbox

This example provides instructions for reading the IP_TYPE and IP_INSTANCE_ID of all the interfaces in the IO96B using the mailbox.

The values shown below are for illustrative purposes and are obtained from an EMIF example design using DDR4 x32 + ECC implemented on the Agilex™ 7 FPGA E-Series 065B Development Kit - Premium. This configuration uses the Primary MC of the Primary IO96B.

Base address for mailbox=0x500_0000

Address for each mailbox register = Base address + offset of each register

The following table shows the addresses for the mailbox registers.

Table 210.  Addresses for Mailbox Registers
Register Name Byte Offset (Decimal) Byte Offset (Hex) Address (Hex)
STATUS 1024 0x400 0x5000400
CMD_PARAM_6 1056 0x420 0x5000420
CMD_PARAM_5 1060 0x424 0x5000424
CMD_PARAM_4 1064 0x428 0x5000428
CMD_PARAM_3 1068 0x42C 0x500042c
CMD_PARAM_2 1072 0x430 0x5000430
CMD_PARAM_1 1076 0x434 0x5000434
CMD_PARAM_0 1080 0x438 0x5000438
CMD_REQ 1084 0x43c 0x500043c
CMD_RESPONSE_DATA_2 1104 0x450 0x5000450
CMD_RESPONSE_DATA_1 1108 0x454 0x5000454
CMD_RESPONSE_DATA_0 1112 0x458 0x5000458
CMD_RESPONSE_STATUS 1116 0x45c 0x500045c

The table below illustrates the construction of the data to be written to the CMD_REQ register for this request:

CMD_REQ [31:29]:

CMD_TARGET_IP_TYPE

CMD_REQ [28:24]:

CMD_TARGET_IP_INSTANCE_ID

CMD_REQ [23:16]:

CMD_TYPE

CMD_REQ [15:0]:

CMD_OPCODE

CMD_REQ [31:0]:

0x0 (not used)

0x0 (not used)

 0x01 (CMD_GET_SYS_INFO) 0x0001(GET_MEM_INTF_INFO)

0x0001_0001

Follow these steps to send the Command using the JAMB/AXI-Lite interface for the interface:

  1. It is not required to write to the CMD_PARAM_* register as this OPCODE does not require any cmd_param .
  2. Write to the CMD_REQ(address=0x500_043c) with write_data=0x0001_0001 .
  3. Read from CMD_RESPONSE_STATUS(address=0x500_045c) until you get the STATUS_COMMAND_RESPONSE_READY (Bit 0 of CMD_RESPONSE_STATUS register) equals to 1 .

    The expected read data=0x0001_0001, where:

    The first 1 indicates that CMD_RESPONSE_DATA_SHORT[1:0]=1 , indicating that only one memory interface is instantiated in this IO96B.

    The second 1 is STATUS_CMD_RESPONSE_READY.

  4. Read from CMD_RESPONSE_DATA_0(address=0x500_0458).

    The expected read_data=0x2000_0000.

    IP_TYPE for interface 0 = CMD_RESPONSE_DATA_0 [31:29]= 0x1 , indicating interface 0 is using Primary MC of Primary IO96B.

    IP_INSTANCE_ID for interface 0 = CMD_RESPONSE_DATA_0 [38:24]= 0x0 .

  5. Read from CMD_RESPONSE_DATA_1(address=0x500_0454).

    Expected read_data=0x0000_0000.

    IP_TYPE for interface 1 = CMD_RESPONSE_DATA_1 [31:29]= 0x0 , indicating interface 1 does not exist.

    IP_INSTANCE_ID for interface 1 = CMD_RESPONSE_DATA_1 [38:24]= 0x0.

  6. Clear the STATUS_COMMAND_RESPONSE_READY (Bit 0 of CMD_RESPONSE_STATUS register). Perform a Read-Modify-Write operation:
    1. Read from CMD_RESPONSE_STATUS register.
    2. Write_Data = Data in (a) & 0xffff_fffe (Change only bit 0).
    3. Write to address = 0x500_045c data= write_data from (b).
Level Two Title