2. FPGA AI Suite New Features and Enhancements
FPGA AI Suite Version 2025.3.1 adds the following new features and enhancements:
- Increased the free inference limit for unlicensed IP to 100,000 inferences.
- Added public beta support for writing layout transform results to external memory.
With this feature, the FPGA AI Suite IP layout transform module can write its results directly to DDR memory instead of the stream buffer. Directly writing to DDR memory helps reduce the stream buffer size because the stream buffer no longer needs to be large enough to hold the entire input feature when hardware layout transform is enabled.
- Added a new example design to demonstrate the capability of the layout transform to write results to external memory. This example includes input and output feature streaming, on-chip parameters, and a DDR connection to the FPGA AI Suite IP.