FPGA AI Suite Version 2025.1 adds the following new features and enhancements:

• The performance estimator can now take DDR bandwidth into account. This is specified by passing the --fassumed-memory-bandwidth option into the dla_compiler command and the -ddr_bw into dla_benchmark.
• Bilinear upsampling and downsampling are now supported.
• Improved the accuracy of the software emulator on some graphs.
• When enabled, the layout transform can now apply scale and bias values directly onto the incoming data. Refer to the FPGA AI Suite IP Reference Manual for details.
• The .ptc file produced by the area model for an Agilex™ 5 architecture no longer produces a "PTC Import Warning".
• Beta-level support for Agilex™ 3 devices.

Design Examples

• The SoC streaming-to-memory (S2M) design example on the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit now uses the layout transform provided by the FPGA AI Suite IP rather than an external layout transform.
• Support for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit in design examples has been replaced with support for the Agilex™ 5 FPGA E-Series 065B Modular Development Kit.

• Enhanced the SoC design example (M2M and S2M) with Agilex™ 5 support.

  Agilex™ 5 support in the SoC design example targets the Agilex™ 5 FPGA E-Series 065B Modular Development Kit.