FPGA AI Suite Version 2025.1 has the following known issues:

• The hostless design examples that use JTAG for host-FPGA communication may see a "claim_service: Path cannot be found" error.
  The workaround is to reprogram the FPGA and lower the JTAG clock frequency to a lower frequency, such as 16 MHz, with a command similar to the following example command:

  jtagconfig --setparam 1 JtagClock 16M

• The build example design flow might generate bitstreams with timing failures for the Agilex™ 5 hostless JTAG design examples. Inference performed on such bitstreams hangs.
  When such faulty bitstreams are generated, the dla_adjust_pll.log log file found under the hw subfolder of the Quartus build directory contains the following error message:

  Error (23098): One or more blocks are configured incorrectly and will not have 
  the desired functionality

  To work around this issue, relaunch the example design compilation with a different seed.

• The hostless DDR-free design example Quartus® Prime System Console script generates performance counter values that are displayed with a prefix that indicates that the value is a hexadecimal number. Despite the hexadecimal prefix, the value displayed is a decimal value.

Streaming Flow Known Issues

Multilane Known Issues

• The num_lanes parameter takes only the values 1, 2, or 4.
• Multilane exhibits low performance when used with DDR when a graph has residual connections.

OpenVINO Open Model Zoo Known Issues

ValueError: Invalid filepath extension for saving. Please add either 
a `.keras` extension for the native Keras format (recommended) or 
a `.h5` extension. 
Use `model.export(filepath)` if you want to export a SavedModel for 
use with TFLite/TFServing/etc.

For a workaround, refer to "Preparing a Model" in FPGA AI Suite Getting Started Guide .