2. FPGA AI Suite New Features and Enhancements
FPGA AI Suite Version 2024.1 adds the following new features and enhancements:
- The SoC Design Example has been updated to use Quartus® Prime Version 23.4.
- The Arria® 10 SoC Design Example now supports latest revision of the Arria® 10 SX SoC FPGA Development Kit: DK-SOC-10AS066S-E. This is Rev E of the development kit. Earlier releases of the FPGA AI Suite supported only DK-SOC-10AS066S-D (Rev D) and earlier.
- The FPGA AI Suite IP supports Ubuntu 22.04. The PCIe-attach designs still require Ubuntu 18.04 ( Intel® PAC with Arria® 10 GX FPGA) and Ubuntu 20.04 ( Terasic* DE10-Agilex Development Board).
- A dedicated hardware module to accelerate depthwise layers is now available. This module is documented in the IP Reference Manual. An example .arch file using this module is included as AGX7_Performance_Giant.arch. This module significantly improves inference performance on large IP instances for graphs such as MobileNet.
- You can now configure the IP with a c_vector of 64. This specifies the length of the dot product within the internal arithmetic unit. The previous maximum c_vector was 32. This increase, from 32 to 64, enables larger, higher-performance, instantiations of the inference IP.
- Sigmoid and swish are available as (optional) hardware modules. Previously, sigmoid and swish layers were always sent to the CPU for execution.
- Early access to a hardware-accelerated layout transform module is available. This layout transform module enables input padding and folding to happen on the FPGA, and is beneficial for flows that stream data directly to the IP (rather than from a host). The early access limitations are described in Known Issues and Workarounds.