2. Intel® FPGA AI Suite New Features and Enhancements
This release adds a new example design for the Intel® Arria® 10 SX SoC FPGA Development Kit. This new example design demonstrates how to use the Arm* SoC as host for the Intel® FPGA AI Suite, as well as how to perform inference in a streaming data flow.
In addition, this release adds the following new features:
| New graph |
The I3D model is now accelerated on the FPGA device up to and including the final softmax layer |
| New layer | depth-to-space |
| New FPGA device support | Intel® Stratix® 10 support is now considered production quality |
| New operating system support | Red Hat* Enterprise Linux* 8.7 is now supported |
| New numeric precision | INT8 quantization is now supported via the NNCF framework |
For area-optimized IP, the architecture configuration (.arch) file now contains that disables the debug network. Disabling the debug network reduces the IP area by as much as several thousand ALMs, depending on the configuration of the IP.