Intel® FPGA AI Suite: IP Reference Manual

ID 768974
Date 7/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Multiple Input Graphs

For graphs with more than one input, each tensor is structured as described in the previous section. The multiple input tensors must be packed together at address offsets as reported by the Intel® FPGA AI Suite compiler.

The compiler generates CSV files that describe the input and output tensor, unless you specify the --fno-transform-tables option. Each row of the CSV file gives information about one input. For more details, refer to the Intel® FPGA AI Suite Compiler Reference Manual .

For multiple inputs, the inputs are stored by batch and then by input number. For example, for 3 inputs and 2 batches, the input tensors would be stored as follows:
  • input 1, batch 1
  • input 1, batch 2
  • input 2, batch 1
  • input 2, batch 2
  • input 3, batch 1
  • input 3, batch 2