Intel® FPGA AI Suite: Compiler Reference Manual

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ID 768972
Date 12/01/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite Compiler Reference Manual 2. About the Intel® FPGA AI Suite Compiler 3. Intel® FPGA AI Suite Compiler Use Modes 4. Intel® FPGA AI Suite Compiler Command Line Options A. Intel® FPGA AI Suite Compiler Reference Manual Archives B. Intel® FPGA AI Suite Compiler Reference Manual Document Revision History
3. Intel® FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Estimating the Performance of a Graph 3.3. Estimating the Performance of a Partition of a Graph 3.4. Estimating the Area of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. Intel® FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options) 4.9. Input File Formats for dla_compiler Command 4.10. Generation of Output File Formats 4.11. The Partitioning Table Report
1. Intel® FPGA AI Suite Compiler Reference Manual
2. About the Intel® FPGA AI Suite Compiler
3. Intel® FPGA AI Suite Compiler Use Modes
4. Intel® FPGA AI Suite Compiler Command Line Options
A. Intel® FPGA AI Suite Compiler Reference Manual Archives
B. Intel® FPGA AI Suite Compiler Reference Manual Document Revision History

3.5. Generating an Optimized Architecture

You can generate an optimized architecture in two ways: optimize the architecture for the highest performance subject to a constraint on the maximum allowable FPGA area or optimize the architecture for the smallest possible FPGA area subject to a constraint on the minimum target frame rate (fps).

Section Content
Generating an Architecture for Highest Performance
Generating an Architecture Optimized for a Frame Rate Target Value

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