Intel® FPGA AI Suite: Compiler Reference Manual

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ID 768972
Date 12/01/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite Compiler Reference Manual 2. About the Intel® FPGA AI Suite Compiler 3. Intel® FPGA AI Suite Compiler Use Modes 4. Intel® FPGA AI Suite Compiler Command Line Options A. Intel® FPGA AI Suite Compiler Reference Manual Archives B. Intel® FPGA AI Suite Compiler Reference Manual Document Revision History
3. Intel® FPGA AI Suite Compiler Use Modes x
3.1. Compiling a Graph 3.2. Estimating the Performance of a Graph 3.3. Estimating the Performance of a Partition of a Graph 3.4. Estimating the Area of an Architecture 3.5. Generating an Optimized Architecture
3.5. Generating an Optimized Architecture x
3.5.1. Generating an Architecture for Highest Performance 3.5.2. Generating an Architecture Optimized for a Frame Rate Target Value
4. Intel® FPGA AI Suite Compiler Command Line Options x
4.1. Inputs (dla_compiler Command Options) 4.2. Outputs (dla_compiler Command Options) 4.3. Reporting (dla_compiler Command Options) 4.4. Compilation Options (dla_compiler Command Options) 4.5. Architecture Options (dla_compiler Command Options) 4.6. Architecture Optimizer Options (dla_compiler Command Options) 4.7. Analyzer Tool Options (dla_compiler Command Options) 4.8. Miscellaneous Options (dla_compiler Command Options) 4.9. Input File Formats for dla_compiler Command 4.10. Generation of Output File Formats 4.11. The Partitioning Table Report
1. Intel® FPGA AI Suite Compiler Reference Manual
2. About the Intel® FPGA AI Suite Compiler
3. Intel® FPGA AI Suite Compiler Use Modes
4. Intel® FPGA AI Suite Compiler Command Line Options
A. Intel® FPGA AI Suite Compiler Reference Manual Archives
B. Intel® FPGA AI Suite Compiler Reference Manual Document Revision History

3.3. Estimating the Performance of a Partition of a Graph

When the Intel® FPGA AI Suite performs inference for a given machine learning graph by assigning some layers to the FPGA device and some layers to the CPU, the graph is divided into subgraphs. Each subgraph represents a portion of the original graph that executes wholly on the CPU or executes wholly on the FPGA. It is possible to estimate the performance of an individual FPGA subgraph.

To estimate the performance of a subgraph, use the --est-fps-single-subgraph option.

The dla_compiler command compiles the graph for the specified architecture to estimate subgraph performance.

The list of required and optional arguments includes all the required and optional arguments from Compiling a Graph . In addition, the following options are specific to estimating subgraph performance:

Option

Description
--est-fps-single-subgraph [Required] Enables the subgraph performance estimator.
--est-fps-subgraph-index= <subgraph index> [Required] Specifies the subgraph index.
--est-fps-network-index= <network index> [Optional] Specifies the network index (in case multiple network files were passed to the dla_compiler command).
--fassumed-fmax-core=<assumed fMAX> [Optional] Specifies the assumed fMAX of the compiled IP.

The performance estimator does not have the ability to estimate fMAX of a given IP parameterization, nor does it know which speed grade the IP targets. Typically, the IP achieves 300 MHz or higher on a C2 Intel® Arria® 10 device.

The default fMAX is chosen based on the family parameter value in the architecture description file (.arch).

The estimated frame rate (fps) of the subgraph is displayed in the terminal.

The simplest command format for estimating the performance of a subgraph is as follows: 

dla_compiler \
   --est-fps-single-subgraph \
   --est-fps-subgraph-index <index> \
   --network-file <path to graph.xml> \
   --march <path to .arch file>

Example Command

dla_compiler \
   --est-fps-single-subgraph \
   --est-fps-subgraph-index=0 \
   --est-fps-network-index=0 \
   --network-file ResNet50.xml MobileNet_v2.xml \
   --march $COREDLA_ROOT/example_architectures/A10_Generic.arch \
   --fassumed-fmax-core=300
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