Intel® FPGA AI Suite: Getting Started Guide

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ID 768970
Date 7/17/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA AI Suite Getting Started Guide 2. Intel® FPGA AI Suite Components 3. Intel® FPGA AI Suite Installation Overview 4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools 5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites 6. Intel® FPGA AI Suite Quick Start Tutorial A. Intel® FPGA AI Suite Getting Started Guide Archives B. Intel® FPGA AI Suite Getting Started Guide Document Revision History
3. Intel® FPGA AI Suite Installation Overview x
3.1. Intel® FPGA AI Suite Directory Structure
4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools x
4.1. Supported FPGA Families 4.2. Operating System Prerequisites 4.3. Installing the Intel® FPGA AI Suite With System Package Management Tools 4.4. Installing OpenVINO™ Toolkit 4.5. Installing Intel® Quartus® Prime Pro Edition Software 4.6. Setting Required Environment Variables 4.7. Installing Intel® Threading Building Blocks (TBB) 4.8. Finalizing Your Intel® FPGA AI Suite Installation
4.3. Installing the Intel® FPGA AI Suite With System Package Management Tools x
4.3.1. Installing the Intel® FPGA AI Suite Into an Alternative Location
5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites x
5.1. PCIe-based Design Example Hardware Prerequisites 5.2. PCIe-based Design Example Operating System Prerequisites 5.3. PCIe-based Design Example Software Prerequisites
5.3. PCIe-based Design Example Software Prerequisites x
5.3.1. Additional Software Prerequisites for the PCIe-based Design Example for Intel Agilex® 7 Devices 5.3.2. Additional Software Prerequisites for the PCIe-Based Design Example for Intel® Arria® 10 Devices
6. Intel® FPGA AI Suite Quick Start Tutorial x
6.1. Creating a Working Directory 6.2. Preparing OpenVINO™ Model Zoo 6.3. Preparing a Model 6.4. Running the Graph Compiler 6.5. Preparing an Image Set 6.6. Programming the FPGA Device 6.7. Performing Inference on the PCIe-Based Example Design 6.8. Building an FPGA Bitstream for the PCIe Example Design 6.9. Building the Example FPGA Bitstreams 6.10. Preparing a ResNet50 v1 Model 6.11. Performing Inference on the Inflated 3D (I3D) Graph 6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics
6.12. Performing Inference on YOLOv3 and Calculating Accuracy Metrics x
6.12.1. Preparing a YOLOv3 Model 6.12.2. Preparing a COCO Validation Dataset and Annotations 6.12.3. Inference on YOLOv3 and Calculating Accuracy Scores
1. Intel® FPGA AI Suite Getting Started Guide
2. Intel® FPGA AI Suite Components
3. Intel® FPGA AI Suite Installation Overview
4. Installing the Intel® FPGA AI Suite Compiler and IP Generation Tools
5. Installing the Intel® FPGA AI Suite PCIe-Based Design Example Prerequisites
6. Intel® FPGA AI Suite Quick Start Tutorial
A. Intel® FPGA AI Suite Getting Started Guide Archives
B. Intel® FPGA AI Suite Getting Started Guide Document Revision History

6.11. Performing Inference on the Inflated 3D (I3D) Graph

Before you try the instructions in this section, ensure that you have completed the following tasks:
Remember: A model must be converted from a framework (such as Tensorflow, Caffe, or PyTorch) into a .bin/.xml file pair before the Intel® FPGA AI Suite compiler (dla_compiler command) can ingest the model.

Preparing the i3d-rgb-tf Model

The following commands download the i3d-rgb-tf TensorFlow model and run Model Optimizer: 
source ~/build-openvino-dev/openvino_env/bin/activate
omz_downloader --name i3d-rgb-tf \
   --output_dir $COREDLA_WORK/demo/models/
omz_converter --name i3d-rgb-tf \
   --download_dir $COREDLA_WORK/demo/models/ \
   --output_dir $COREDLA_WORK/demo/models/
After running these commands, you can find the model in the following directory: 
demo/models/public/i3d-rgb-tf/FP32/

Inference on the i3d-rgb-tf Model and Accuracy Calculations

This section details how to run inference on i3d-rgb-tf with the sample videos and ground truth files provided. For 3D input, the batch size determines how many "clips" a video should be broken down into.

To run inference on the i3d-rgb-tf model with 3 clips per video, run the following commands: 
cd $COREDLA_WORK/runtime/build_Release/dla_benchmark
gnd=$COREDLA_WORK/demo/sample_videos/groundtruth_batch_size_3.txt
./dla_benchmark \
   -b=3 \
   -niter=4 \
   -m $COREDLA_WORK/demo/models/public/i3d-rgb-tf/FP32/i3d-rgb-tf.xml \
   -d=HETERO:FPGA,CPU \
   -i=$COREDLA_WORK/demo/sample_videos/ \
   -plugins_xml_file=../plugins.xml \
   -arch_file=$curarch \
   -api=async \
   -nireq=4 \
   -perf_est \
   -groundtruth_loc=$gnd \
   -folding_option=1
To run inference on the i3d-rgb-tf model with 1 clip per video, change the ground truth file (-groundtruth_loc) and the -b flag as follows: 
cd $COREDLA_WORK/runtime/build_Release/dla_benchmark
gnd=$COREDLA_WORK/demo/sample_videos/groundtruth_batch_size_1.txt
./dla_benchmark \
   -b=1 \
   -niter=4 \
   -m $COREDLA_WORK/demo/models/public/i3d-rgb-tf/FP32/i3d-rgb-tf.xml \
   -d=HETERO:FPGA,CPU \
   -i=$COREDLA_WORK/demo/sample_videos/ \
   -plugins_xml_file=../plugins.xml \
   -arch_file=$curarch \
   -api=async \
   -nireq=4 \
   -perf_est \
   -groundtruth_loc=$gnd \
   -folding_option=1
Important: Loading the video data with the dla_benchmark command places a high memory demand on the host. Using values for the -niter option that are less than 100 results in manageable memory requirements for most hosts. If the memory usage is too high, the operating system might abruptly end the running dla_benchmark command.
Ground truth files are included for both 3 clips per video, and 1 clip per video. To use a different number of clips per video:
  1. Create a new ground truth text file that contains the correct action class for each video being repeated the same amount of time as the amount of clips per video

    See the groundtruth_batch_size_3.txt file for reference. The ground truths are repeated 3 times each in that file.

  2. Change the -groundtruth_loc option to point to the new ground truth text file that you created.

To run the dla_benchmark command on the CPU, change the ‑d=HETERO:FPGA,CPU option to ‑d=HETERO:CPU.

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