Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide
ID
768844
Date
7/14/2025
Public
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs
3. NoC Design Flow in Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide
2.6.1. Determining the Number of NoC Targets
2.6.2. Determining the Number of NoC Initiators
2.6.3. Fabric NoC Considerations
2.6.4. Latency Considerations
2.6.5. Initiator and Target Bandwidth Considerations
2.6.6. Horizontal Bandwidth Considerations
2.6.7. Options for Managing NoC Bandwidth
2.6.8. GPIO-B Bypass Mode and Initiators
3.4.1. General NoC IP Connectivity Guidelines
3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers
3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers
3.4.4. Connectivity Guidelines: NoC Clock Control
3.4.5. Connectivity Guidelines: NoC Initiators for HPS
3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces
7.1.2.2. NoC Initiator AXI4 User Interface Signals
7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals
7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals
7.1.2.5. NoC Initiator IP Platform Designer-Only Signals
7. Hard Memory NoC IP Reference
This chapter provides interface, signal, and parameter information for the NoC Initiator Intel FPGA IP and the NoC Clock Control Intel FPGA IP. The targets for the hard memory NoC in Agilex™ 7 M-Series FPGAs are part of the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP or the External Memory Interfaces (EMIF) IP.
For information on NoC targets in the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP, refer to the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 M-Series FPGA IP User Guide.
For information on NoC targets in external memory interfaces, refer to the External Memory Interfaces Agilex™ 7 M-Series FPGA IP User Guide.