Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide
ID
768844
Date
7/14/2025
Public
Answers to Top FAQs
1. Network-on-Chip (NoC) Overview
2. Hard Memory NoC in Agilex™ 7 M-Series FPGAs
3. NoC Design Flow in Quartus® Prime Pro Edition
4. NoC Real-time Performance Monitoring
5. Simulating NoC Designs
6. NoC Power Estimation
7. Hard Memory NoC IP Reference
8. Document Revision History of Agilex™ 7 M-Series FPGA Network-on-Chip (NoC) User Guide
2.6.1. Determining the Number of NoC Targets
2.6.2. Determining the Number of NoC Initiators
2.6.3. Fabric NoC Considerations
2.6.4. Latency Considerations
2.6.5. Initiator and Target Bandwidth Considerations
2.6.6. Horizontal Bandwidth Considerations
2.6.7. Options for Managing NoC Bandwidth
2.6.8. GPIO-B Bypass Mode and Initiators
3.4.1. General NoC IP Connectivity Guidelines
3.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers
3.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers
3.4.4. Connectivity Guidelines: NoC Clock Control
3.4.5. Connectivity Guidelines: NoC Initiators for HPS
3.4.6. Connectivity Guidelines: NoC Targets for HPS
3.5.4.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator
3.5.4.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator
3.5.4.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator
3.5.4.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator
3.5.4.5. Example 5: Hard Processor System with Two External Memory Interfaces
7.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces
7.1.2.2. NoC Initiator AXI4 User Interface Signals
7.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals
7.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals
7.1.2.5. NoC Initiator IP Platform Designer-Only Signals
5.1.1. Generating the Abstract Simulation Include File (Platform Designer Connection Flow)
To generate the abstract simulation include file in the Platform Designer connection flow, follow these steps:
- Connect the AXI4 NoC manager ports to the AXI4 NoC subordinate ports in the System View tab of Platform Designer. The AXI4 NoC manager ports are on the NoC Initiator Intel FPGA IP. The AXI4 NoC subordinate ports are on the High Bandwidth Memory (HBM2E) Interface Agilex™ 7 FPGA IP and on the External Memory Interfaces (EMIF) IP.
- Click the Address Map tab in Platform Designer to assign base addresses for each NoC initiator to target connection. If an initiator connects to multiple targets, ensure that each target has a unique starting address. For NoC connections, you only need to specify the starting address. Specifying the ending address for NoC connections is unnecessary.
For HBM2e memory, the minimum address span is 1 GB and you must align base addresses to 1 GB boundaries. For external memory interfaces, the minimum address span is 4 GB and you must align base addresses to 4 GB boundaries. For example, if an initiator connects to both HBM2e memory and DDR5 memory, you can specify the base address for the HBM2e memory as 0x00000000, and specify the base address for the DDR5 memory as 0x40000000, assuming a 16 GB HBM2e memory space.
- Save the system and click Generate HDL. Platform Designer generates the registration include file along with the HDL. There is no need to run Quartus® Prime Analysis & Elaboration before simulation when using this flow.
If you update any initiator-to-target connections or address mapping in Platform Designer, you must click Generate HDL to update the simulation include file.
Related Information