F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
ID
758946
Date
3/31/2025
Public
1. About the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
7.2. RX MAC Interface to User Logic
The user interface for the MAC receive direction is a Avalon® streaming interface. A valid FCS for a packet results in the l1_rx_error bit 1 being low when l1_rx_endofpacket is high. An FCS violation is indicated when the l1_rx_error bit 1 is high and when the l1_rx_endofpacket is high.
Signal |
Direction |
Description |
---|---|---|
clk_rxmac | Output | rx_pcs_ready is asserted. The frequency of this clock is 390.625 MHz. All RX MAC interface signals are synchronous to clk_rxmac . |
l1_rx_data[127:0] | Output | Data output from the MAC. Bit[127] is the MSB and bit[0] is the LSB. Bytes are read in the usual left to right order. The IP reverses the byte order to meet the requirements of the Ethernet standard. Clock for the RX MAC. Recovered from the incoming data. This clock is guaranteed stable when null. |
l1_rx_valid | Output | When asserted, indicates that l1_rx_data[63:0] is driving valid data. When this signal is low,l1_rx_data, l1_rx_startofpocket, l1_rx_endofpacket, l1_rx_empty, and l1_rx_error are ignored. |
l1_rx_startofpacket | Output | When asserted, indicates the first byte of a frame. |
l1_rx_endofpacket | Output | When asserted, indicates the last data byte of a frame before the frame check sequence (FCS). In CRC pass-through mode, it is the last byte of the FCS. The packet can end at any byte position. |
l1_rx_empty[2:0] | Output | Specifies the number of empty bytes when l1_rx_endofpacket is asserted. The packet can end at any byte position. The empty bytes are the low-order bytes. |
l1_rx_error[5:0] | Output | When asserted in the same cycle as l1_rx_endofpacket, indicates the current packet should be treated as an error packet. The 6 bits of l1_rx_error specify the following errors:
|
l1_rxstatus_valid | Output | When asserted, indicates that l1_rxstatus_data is driving valid data. |
l1_rxstatus_data[39:0] | Output | Specifies information about the received frame. The following fields are defined:
|
pause_receive_rx[FCQN-1:0] | Output | This signal is available if you turn on Enable flow control in the parameter editor. Each bit of pause_receive_rx[FCQN-1:0] indicates that the corresponding queue is being paused. |
Figure 20. 50G Ethernet Intel FPGA IP MAC to Client Avalon® Streaming Interface l1_rx_data reception order is highest byte to lowest byte. The first byte of the destination address is on l1_rx_data[63:56] , 0xfbe4 . . . in this timing diagram.