1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile 25G Ethernet IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. F-Tile 25G Ethernet IP User Guide Archive
10. Document Revision History for the F-Tile 25G Ethernet IP User Guide
7.1. TX MAC Interface to User Logic
7.2. RX MAC Interface to User Logic
7.3. Transceivers
7.4. Transceiver Reconfiguration Signals
7.5. Avalon® Memory-Mapped Management Interface
7.6. Dynamic Reconfiguration Interface Signals
7.7. Miscellaneous Status and Debug Signals
7.8. Clock Signals
7.9. Reset Signals
3.5.3. Placement Settings for the F-Tile 25G Ethernet IP Core
The Quartus Prime software provides the options to specify design partitions and Logic Lock (Standard) or Logic Lock regions for incremental compilation, to control placement on the device. To achieve timing closure for your design, you might need to provide floorplan guidelines using one or both of these features.
The appropriate floorplan is always design-specific, and depends on your design.
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