1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile 25G Ethernet IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. F-Tile 25G Ethernet IP User Guide Archive
10. Document Revision History for the F-Tile 25G Ethernet IP User Guide
7.1. TX MAC Interface to User Logic
7.2. RX MAC Interface to User Logic
7.3. Transceivers
7.4. Transceiver Reconfiguration Signals
7.5. Avalon® Memory-Mapped Management Interface
7.6. Dynamic Reconfiguration Interface Signals
7.7. Miscellaneous Status and Debug Signals
7.8. Clock Signals
7.9. Reset Signals
3.3. Simulating the IP Core
You can simulate your F-Tile 25G Ethernet IP core variation with the functional simulation model and the testbench generated with the IP core. The functional simulation model is a cycle-accurate model that allows for fast functional simulation of your IP core instance using industry-standard Verilog HDL simulators. You can simulate the Altera-provided testbench or create your own testbench to exercise the IP core functional simulation model.
The functional simulation model and testbench files are generated in project subdirectories. These directories also include scripts to compile and run the design example.
Note: Use the simulation models only for simulation and not for synthesis or any other purposes. Using these models for synthesis creates a nonfunctional design.