1. About the F-Tile Triple-Speed Ethernet IP User Guide
2. About F-Tile Triple-Speed Ethernet IP
3. Getting Started
4. Parameter Settings
5. Functional Description
6. Configuration Register Space
7. Interface Signals
8. Design Considerations
9. Timing Constraints
10. Software Programming Interface
11. F-Tile Triple-Speed Ethernet IP User Guide Archives
12. Document Revision History for the F-Tile Triple-Speed Ethernet IP User Guide
A. Ethernet Frame Format
B. Simulation Parameters
5.1.1. MAC Architecture
5.1.2. MAC Interfaces
5.1.3. MAC Transmit Datapath
5.1.4. MAC Receive Datapath
5.1.5. MAC Transmit and Receive Latencies
5.1.6. FIFO Buffer Thresholds
5.1.7. Congestion and Flow Control
5.1.8. Magic Packets
5.1.9. MAC Local Loopback
5.1.10. MAC Reset
5.1.11. PHY Management (MDIO)
5.1.12. Connecting MAC to External PHYs
6.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17)
6.1.2. Statistics Counters (Dword Offset 0x18 – 0x38)
6.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)
6.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7)
6.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)
6.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3)
6.1.7. IEEE 1588v2 Feature PMA Delay
7.1.1. 10/100/1000 Ethernet MAC Signals
7.1.2. 10/100/1000 Multiport Ethernet MAC Signals
7.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
7.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (F-Tile)
7.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
7.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 , 1000BASE-X/SGMII 2XTBI PCS, and Embedded Serial PMA Signals
7.1.7. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
7.1.8. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
7.1.9. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
7.1.10. 1000BASE-X/SGMII PCS Signals
7.1.11. 1000BASE-X/SGMII 2XTBI PCS Signals
7.1.12. 1000BASE-X/SGMII PCS and PMA Signals
7.1.1.1. Clock and Reset Signals
7.1.1.2. Clock Enabler Signals
7.1.1.3. MAC Control Interface Signals
7.1.1.4. MAC Status Signals
7.1.1.5. MAC Receive Interface Signals
7.1.1.6. MAC Transmit Interface Signals
7.1.1.7. Pause and Magic Packet Signals
7.1.1.8. MII/GMII/RGMII Signals
7.1.1.9. PHY Management Signals
7.1.1.10. ECC Status Signals
7.1.6.1. Deterministic Latency Clock Signals
7.1.6.2. IEEE 1588v2 RX Timestamp Signals
7.1.6.3. IEEE 1588v2 TX Timestamp Signals
7.1.6.4. IEEE 1588v2 TX Timestamp Request Signals
7.1.6.5. IEEE 1588v2 TX Insert Control Timestamp Signals
7.1.6.6. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals
7.1.6.7. IEEE 1588v2 PCS Phase Measurement Clock Signal
10.6.1. alt_tse_mac_get_common_speed()
10.6.2. alt_tse_mac_set_common_speed()
10.6.3. alt_tse_phy_add_profile()
10.6.4. alt_tse_system_add_sys()
10.6.5. triple_speed_ethernet_init()
10.6.6. tse_mac_close()
10.6.7. tse_mac_raw_send()
10.6.8. tse_mac_setGMII mode()
10.6.9. tse_mac_setMIImode()
10.6.10. tse_mac_SwReset()
3.4. IP Core Generation Output
The Quartus® Prime software generates the following output file structure for individual IP cores that are not part of a Platform Designer system.
Figure 15. Individual IP Core Generation Output
File Name | Description |
---|---|
<your_ip>.ip | Top-level IP variation file that contains the parameterization of an IP core in your project. If the IP variation is part of a Platform Designer system, the parameter editor also generates a .qsys file. |
<your_ip>.cmp | The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you use in VHDL design files. |
<your_ip>_generation.rpt | IP or Platform Designer generation log file. Displays a summary of the messages during IP generation. |
<your_ip>.qgsimc (Platform Designer systems only) | Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL. |
<your_ip>.qgsynth (Platform Designer systems only) | Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL. |
<your_ip>.qip | Contains all information to integrate and compile the IP component. |
<your_ip>.csv | Contains information about the upgrade status of the IP component. |
<your_ip>.bsf | A symbol representation of the IP variation for use in Block Diagram Files (.bdf). |
<your_ip>.spd | Input file that ip-make-simscript requires to generate simulation scripts. The .spd file contains a list of files you generate for simulation, along with information about memories that you initialize. |
<your_ip>.ppf | The Pin Planner File (.ppf) stores the port and node assignments for IP components you create for use with the Pin Planner. |
<your_ip>_bb.v | Use the Verilog blackbox (_bb.v) file as an empty module declaration for use as a blackbox. |
<your_ip>_inst.v or _inst.vhd | HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation. |
<your_ip>.regmap | If the IP contains register information, the Quartus® Prime software generates the .regmap file. The .regmap file describes the register map information of host and agent interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console. |
<your_ip>.svd | Allows HPS System Debug tools to view the register maps of peripherals that connect to HPS within a Platform Designer system. During synthesis, the Quartus® Prime software stores the .svd files for agent interface visible to the System Console hosts in the .sof file in the debug session. System Console reads this section, which Platform Designer queries for register map information. For system agents, Platform Designer accesses the registers by name. |
<your_ip>.v <your_ip>.vhd |
HDL files that instantiate each submodule or child IP core for synthesis or simulation. |
mentor/ | Contains a msim_setup.tcl script to set up and run a simulation with a supported Siemens EDA simulator, such as the ModelSim simulator. |
aldec/ | Contains a Riviera-PRO* script rivierapro_setup.tcl to setup and run a simulation. |
/synopsys/vcs /synopsys/vcsmx |
Contains a shell script vcs_setup.sh to set up and run a VCS* simulation. Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up and run a VCS* MX simulation. |
/cadence | Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSim simulation. |
/xcelium | Contains an Xcelium* Parallel simulator shell script xcelium_setup.sh and other setup files to set up and run a simulation. |
/submodules | Contains HDL files for the IP core submodule. |
<IP submodule>/ | Platform Designer generates /synth and /sim sub-directories for each IP submodule directory that Platform Designer generates. |