MACsec Intel® FPGA IP User Guide

ID 736108
Date 4/03/2023

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Document Table of Contents

9. Document Revision History for the MACsec Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.04.03 23.1 1.4.0
  • Added the Simulation Requirements section in the chapter MACsec IP Example Design.
  • In the MACsec IP Parameter Settings table, added the Snapshot Enable parameter.
  • Updated the register map with the snapshot control register information.
  • Updated the Port Configurations section in the chapter MACsec IP Example Design.
  • Updated the MACsec IP Parameters Settings table.
  • Updated product family name to Intel Agilex 7.
2022.12.19 22.4 1.3.0
  • Added more description in the section SmartNIC.
  • Updated the Resource Utilization table.
  • Consolidated the "last_segment*" signals in all the interface tables and waveforms in the Interfaces chapter.
  • Updated the figure MACsec Intel FPGA IP Clock Domain
  • Updated the table MACsec Intel FPGA IP Parameter Settings.
  • Updated the table Available MACsec Design Example Variant.
  • Updated the table Clocking Parameters.
  • Removed the section MACsec Software Rekeying.
  • Added a new section Switching Port Muxes between Store and Forward and Cut-Through Modes
  • Updated the Register Map by removing 3 registers.
  • Made other miscellaneous changes throughout the manual.
2022.10.21 22.3 1.2.0 Initial release.