Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
ID
730783
Date
11/25/2024
Public
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1. About the RiscFree* IDE
2. Getting Started with the Ashling* RiscFree* IDE for Intel® FPGAs
3. Using Ashling* RiscFree* IDE for Intel® FPGAs with Nios® V Processor System
4. Using Ashling* RiscFree* IDE for Intel® FPGAs with Arm* Hard Processor System
5. Debugging Features with RiscFree* IDE for Intel® FPGAs
6. Debugging with Command-Line Interface
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix
3.1. Importing Nios® V Processor Project
3.2. Building Nios® V Processor Project
3.3. Setting Run Configuration to Download Nios® V Processor Project
3.4. Setting Debug Configuration to Debug Nios® V Processor Project
3.5. Setting Debug Configuration to Debug a Booting Nios® V Processor Project
3.6. Debugging Tools
5.1. Debug Features in RiscFree* IDE
5.2. Processor System Debug
5.3. Heterogeneous Multicore Debug
5.4. Debugging µC/OS-II Application
5.5. Debugging FreeRTOS Application
5.6. Debugging Zephyr Application
5.7. Arm* HPS On-Chip Trace
5.8. Debugging the Arm* Linux Kernel
5.9. Debugging Target Software in an Intel® Simics Simulator Session
1. About the RiscFree* IDE
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Intel® Quartus® Prime Design Suite 24.3 |
RiscFree* is Ashling’s Eclipse* C/C++ Development Toolkit (CDT) based integrated development environment (IDE) for Intel® FPGAs Arm* -based HPS and RISC-V based Nios® V processors.
The RiscFree* IDE provides a complete, seamless environment for C and C++ software development and has the following features:
- Eclipse* CDT based IDE with full source and project creation, editing, build, and debug support using the RISC-V GNU compiler collection (GCC) toolchain.
- Project Manager and Build Manager including Make and CMake support with rapid import, build, and debug of application frameworks created using the Quartus® Prime software.
- RISC-V GNU GCC toolchain with support for newlib or picolibc run-time libraries using the Nios® V Hardware Abstraction Layer (HAL) API for hardware access.
- Integrated support for Intel® FPGA Download Cable II JTAG debug probe.
- ROM or RAM based debugging support, for example, hardware breakpoints for flash-based support.
- High-level Register Viewer based on industry standard System View Description (SVD) files.
- Integrated serial terminal.