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2.1. FPGA Simulation Essential Elements
2.2. Overview of Simulation Tool Flow
2.3. Simulation Tool Flow
2.4. Supported Hardware Description Languages
2.5. Supported Simulation Types
2.6. Supported Simulators
2.7. Automating Simulation with the Run Simulation Feature
2.8. Using Precompiled Simulation Libraries
2.7.3.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
2.7.3.2. Optional Simulation Settings for Run Simulation (Batch Mode)
2.7.3.3. Launching Simulation with the Run Simulation Feature
2.7.3.4. Running RTL Simulation using Run Simulation
2.7.3.5. Output Directories and Files for Run Simulation
3.1. Types of Questa*-Intel® FPGA Edition Commands
3.2. Commands to Invoke Questa*-Intel® FPGA Edition
3.3. Commands to Compile, Elaborate, and Simulate
3.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries
3.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation
3.6. Using the Qrun Flow
3.7. Performing RTL Simulation with Questa*-Intel® FPGA Edition
3.8. Performing Gate-Level Simulation with Questa*-Intel® FPGA Edition
3.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library
3.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library (work)
3.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo
3.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro FAST Set to 1
3.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package my_pkg and File foo.sv Imports my_pkg
3.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg
3.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing Waveforms of All Top-Level Signals in the Testbench
3.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while Capturing Waveforms of All Top-Level Signals in the Hierarchy
3.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing Waveforms of Top-Level Design Instance
3.8.1. Post-Synthesis and Post-Fit Netlists for Simulation
3.8.2. Files Required for Gate-Level Simulation
3.8.3. Step 1: Generate Gate-Level Netlists for Simulation
3.8.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level Simulation
3.8.5. Step 3: Determine Elaboration Options for Gate-Level Simulation
3.8.6. Step 4: Assemble and Run the Gate-Level Simulation Script
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2.7.3.4. Running RTL Simulation using Run Simulation
To run RTL Simulation using the Run Simulation feature, follow these steps:
- Set up the Run Simulation feature, as Setting Up the Run Simulation Feature describes.
- If your design includes Altera* IP, you generate the simulation model and setup scripts for IP components and Platform Designer systems when generating HDL for these IP. Click the Generate HDL button and specify Simulation options for model generation. For system and IP generation details, refer to Quartus® Prime Pro Edition User Guide: Platform Designer.
- Click Processing > Start > Start Analysis & Elaboration. The Compilation Dashboard indicates when Analysis & Elaboration completes successfully.
- Run RTL Simulation using one of the following methods:
- In the Quartus® Prime software GUI, click Tools > Run Simulation > RTL Simulation.
- In batch mode, type the following command at the Quartus® Prime Tcl console:
execute_flow -simulation
The Run Simulation feature compiles the simulation libraries and runs your simulator automatically, according to your settings when Setting Up the Run Simulation Feature. The Quartus® Prime software displays simulation output messages from the EDA simulator in the simulator GUI (if launched in GUI mode), or in the terminal.
- Analyze the simulation results in your simulator. Correct any functional errors in your design, testbench, or simulation script files. If necessary, re-simulate your design to verify correct behavior.
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