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4.1. Types of Questa* Intel® FPGA Edition Commands
4.2. Commands to Invoke Questa* Intel® FPGA Edition
4.3. Commands to Compile, Elaborate, and Simulate
4.4. Why You Should Only Use Precompiled Questa Intel FPGA Edition Libraries
4.5. Generating a msim_setup.tcl Simulation Script for RTL Simulation
4.6. Performing RTL Simulation with Questa* Intel® FPGA Edition
4.7. Performing Gate-Level Simulation with Questa* Intel® FPGA Edition
4.3.1.1. Compilation Example 1: Compile File foo.sv into a Logical Library
4.3.1.2. Compilation Example 2: Compile File design1.sv to Default Library (work)
4.3.1.3. Compilation Example 3: Compile All .sv Files into Logical Library foo
4.3.1.4. Compilation Example 4: Compile File foo.sv into Work with Verilog Macro FAST Set to 1
4.3.1.5. Compilation Example 5: File my_pkg.sv Defines SystemVerilog Package my_pkg and File foo.sv Imports my_pkg
4.3.1.6. Compilation Example 6: File my_pkg.sv Defines Systemverilog Package my_pkg and File foo.sv Imports my_pkg
4.3.4.1. Simulation Example 1: Run Simulation Until the End, while Capturing Waveforms of All Top-Level Signals in the Testbench
4.3.4.2. Simulation Example 2: Run Simulation for 30 Milliseconds, while Capturing Waveforms of All Top-Level Signals in the Hierarchy
4.3.4.3. Simulation Example 3: Run Simulation Until the End, while Capturing Waveforms of Top-Level Design Instance
4.7.1. Post-Synthesis and Post-Fit Netlists for Simulation
4.7.2. Files Required for Gate-Level Simulation
4.7.3. Step 1: Generate Gate-Level Netlists for Simulation
4.7.4. Step 2: Identify Simulation Files and Compilation Options for Gate-Level Simulation
4.7.5. Step 3: Determine Elaboration Options for Gate-Level Simulation
4.7.6. Step 4: Assemble and Run the Gate-Level Simulation Script
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4.6.2.1.1. Customizing the Generated Simulation Script
You can customize the msim_setup.tcl simulation script that ip-setup-simulation generates.
You may need to customize the simulation script to pass in non-default compilation options to IP source files. You can accomplish this by setting Tcl variables in your top-level Tcl script, as Passing In Custom Compilation and Elaboration Options for msim_setup.tcl describes.
To obtain specific compilation options for an IP, if any, refer to the Platform Designer generated top-level simulation script for the IP’s example design.