A newer version of this document is available. Customers should click here to go to the newest version.
1. About This Document
2. About the Nios® V Embedded Processor
3. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Pro Edition and Platform Designer
4. Nios® V Processor Software System Design
5. Nios® V Processor Configuration and Booting Solutions
6. Nios® V Processor - Using the MicroC/TCP-IP Stack
7. Nios® V Processor Debugging, Verifying, and Simulating
8. Nios® V Embedded Processor Design Handbook Archives
9. Document Revision History for the Nios® V Embedded Processor Design Handbook
5.1. Introduction
5.2. Linking Applications
5.3. Nios® V Processor Booting Methods
5.4. Introduction to Nios® V Processor Booting Methods
5.5. Nios® V Processor Booting from Configuration QSPI Flash
5.6. Nios V Processor Booting from On-Chip Memory (OCRAM)
5.7. Summary of Nios V Processor Vector Configuration and BSP Settings
7.4.1. Prerequisites
7.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer
7.4.3. Creating Nios V Processor Software
7.4.4. Generating Memory Initialization File
7.4.5. Generating System Simulation Files
7.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
7.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer
To generate simulation files, perform the following steps:
- Start the Intel Quartus Prime software and open the Platform Designer from the Tools menu.
- Open the <your project design>.qsys file.
Note: Ensure that you have completed building your Platform Designer system before generating the simulation models
- In Platform Designer, navigate to Generate > Generate Testbench System.
- On the Generation window, set the following parameters to these values:
- Create testbench Platform Designer system— Standard, BFMs for standard Platform Designer interfaces.
Note: If your system has exported ports other than the clock and reset, choose Standard, BFMs for standard Avalon interfaces.
- Create testbench simulation model—Verilog
- Select Use multiple processors for faster IP generation (when available).
- Create testbench Platform Designer system— Standard, BFMs for standard Platform Designer interfaces.
- Click Generate, and Save, if prompted.
Figure 94. Testbench Generation
