F-Tile JESD204B Intel® FPGA IP User Guide

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ID 723907
Date 1/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile JESD204B IP Quick Reference 2. About the F-Tile JESD204B Intel® FPGA IP 3. Getting Started 4. F-Tile JESD204B IP Functional Description 5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines 6. F-Tile JESD204B IP Debug Guidelines 7. F-Tile JESD204B Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide
2. About the F-Tile JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. F-Tile JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. F-Tile JESD204B IP Design Considerations 3.8. F-Tile JESD204B Intel® FPGA IP Parameters 3.9. F-Tile JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the F-Tile JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. F-Tile JESD204B IP Design Considerations x
3.7.1. Integrating the F-Tile JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Adding External System PLL
4. F-Tile JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. System PLL Clock
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Register Map and Definition 4.7.3. Transmitter Registers 4.7.4. Receiver Registers
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. F-Tile JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. F-Tile JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Transceiver Toolkit
1. F-Tile JESD204B IP Quick Reference
2. About the F-Tile JESD204B Intel® FPGA IP
3. Getting Started
4. F-Tile JESD204B IP Functional Description
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines
6. F-Tile JESD204B IP Debug Guidelines
7. F-Tile JESD204B Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide

4.7.2. Register Map and Definition

Table 20.  Address Table for JESD204 TX Registers
Address Title
0x0 Physical Lane Control Common
0x4 Physical Lane Control 0
0x8 Physical Lane Control 1
0xC Physical Lane Control 2
0x10 Physical Lane Control 3
0x14 Physical Lane Control 4
0x18 Physical Lane Control 5
0x1C Physical Lane Control 6
0x20 Physical Lane Control 7
0x24 - 0x4F -
0x50 Data Link Layer (DLL) and TX Control
0x54 SYNCN and SYSREF Control
0x58 Control Register Reserve
0x5C - 0x5F -
0x60 JESD204 TX Error Status
0x64 JESD204 TX Error Interrupt Enable
0x6C - 0x7F -
0x80 JESD204 TX Status 0
0x84 JESD204 TX Status 1
0x88 JESD204 TX Status 2
0x8C JESD204 TX Status 3
0x90 JESD204 TX ILAS data 0
0x94 JESD204 TX ILAS data 1
0x98 JESD204 TX ILAS data 2
0x9C JESD204 TX ILAS data 3
0xA0 JESD204 TX ILAS data 4
0xA4 JESD204 TX ILAS data 5
0xA8-0xAF -
0xB0 JESD204 TX ILAS data 8
0xB4 JESD204 TX ILAS data 9
0xB8-0xBF
0xC0 JESD204 TX ILAS data 12
0xC4-0xCF -
0xD0 JESD204 TX Test
0xD4 JESD204 TX Test Pattern A
0xD8 JESD204 TX Test Pattern B
0xDC JESD204 TX Test Pattern C
0xE0 JESD204 TX Test Pattern D
0xE4 - 0x3F8 -
0x3FC Unused
Table 21.  Address Table for JESD204 RX Registers
Address Title
0x0 Physical Lane Control Common
0x4 Physical Lane Control 0
0x8 Physical Lane Control 1
0xC Physical Lane Control 2
0x10 Physical Lane Control 3
0x14 Physical Lane Control 4
0x18 Physical Lane Control 5
0x1C Physical Lane Control 6
0x20 Physical Lane Control 7[CACY1]
0x24 - 0x4F -
0x50 Data Link Layer (DLL) and RX Control
0x54 SYNCN and SYSREF Control[CACY2]
0x58 Reserved Control
0x5C - 0x5F -
0x60 JESD204 RX Error Status 0
0x64 JESD204 RX Error Status 1
0x68-0x73[CACY3] -
0x74 JESD204 RX Error Interrupt Enable
0x78 JESD204 RX Error Link Reinitialization Enable
0x7C - 0x7F -
0x80 JESD204 RX Status 0
0x84 JESD204 RX Status 1
0x88 JESD204 RX Status 2
0x8C JESD204 RX Status 3
0x90 – 0x93 -
0x94 JESD204 RX ILAS data 1
0x98 JESD204 RX ILAS data 2
0x9C – 0x9F -
0xA0 JESD204 RX ILAS octet 0
0xA4 JESD204 RX ILAS octet 1
0xA8 JESD204 RX ILAS octet 2
0xAC JESD204 RX ILAS octet 3
0xB0 – 0xBF -
0xC0 JESD204 RX ILAS data 12
0xC4 – 0xCF -
0xD0 JESD204 RX test control
0xD4 – 0xEF -
0xF0 JESD204 RX Status 4
0xF4 JESD204 RX Status 5
0xF8 JESD204 RX Status 6
0xFC JESD204 RX Status 7
0x100-0x3F8 -
0x3FC Unused
Level Two Title