F-Tile JESD204B Intel® FPGA IP User Guide

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ID 723907
Date 5/18/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile JESD204B IP Quick Reference 2. About the F-Tile JESD204B Intel® FPGA IP 3. Getting Started 4. F-Tile JESD204B IP Functional Description 5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines 6. F-Tile JESD204B IP Debug Guidelines 7. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide
2. About the F-Tile JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. F-Tile JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. F-Tile JESD204B IP Design Considerations 3.8. F-Tile JESD204B Intel® FPGA IP Parameters 3.9. F-Tile JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Intel® Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the F-Tile JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. F-Tile JESD204B IP Design Considerations x
3.7.1. Integrating the F-Tile JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Adding External System PLL
4. F-Tile JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. System PLL Clock
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Register Map and Definition 4.7.3. Transmitter Registers 4.7.4. Receiver Registers
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. F-Tile JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. F-Tile JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment
1. F-Tile JESD204B IP Quick Reference
2. About the F-Tile JESD204B Intel® FPGA IP
3. Getting Started
4. F-Tile JESD204B IP Functional Description
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines
6. F-Tile JESD204B IP Debug Guidelines
7. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide

4.7.3. Transmitter Registers

Table 22.  Address Table for JESD204 TX Registers
Address Title
0x0 Physical Lane Control Common
0x4 Physical Lane Control 0
0x8 Physical Lane Control 1
0xC Physical Lane Control 2
0x10 Physical Lane Control 3
0x14 Physical Lane Control 4
0x18 Physical Lane Control 5
0x1C Physical Lane Control 6
0x20 Physical Lane Control 7
0x24 - 0x4F -
0x50 Data Link Layer (DLL) and TX Control
0x54 SYNCN and SYSREF Control
0x58 Control Register Reserve
0x5C - 0x5F -
0x60 JESD204 TX Error Status
0x64 JESD204 TX Error Interrupt Enable
0x6C - 0x7F -
0x80 JESD204 TX Status 0
0x84 JESD204 TX Status 1
0x88 JESD204 TX Status 2
0x8C JESD204 TX Status 3
0x90 JESD204 TX ILAS data 0
0x94 JESD204 TX ILAS data 1
0x98 JESD204 TX ILAS data 2
0x9C JESD204 TX ILAS data 3
0xA0 JESD204 TX ILAS data 4
0xA4 JESD204 TX ILAS data 5
0xA8-0xAF -
0xB0 JESD204 TX ILAS data 8
0xB4 JESD204 TX ILAS data 9
0xB8-0xBF
0xC0 JESD204 TX ILAS data 12
0xC4-0xCF -
0xD0 JESD204 TX Test
0xD4 JESD204 TX Test Pattern A
0xD8 JESD204 TX Test Pattern B
0xDC JESD204 TX Test Pattern C
0xE0 JESD204 TX Test Pattern D
0xE4 - 0x3F8 -
0x3FC Unused
Table 23.  lane_ctrl_commonCommon lane control and assignment. The common lane control applies to all lanes in the link..

Offset: 0x0

Note: The bits that are compile-time specific are not configurable through register. You must recompile to change the value.)
Bit Name Description Attribute Reset
31:4 Reserved Reserved RV 0x0
2 rl Physical lane control reserve register RW 0x0
1 bit_reversal

Bit reversal for LSB/MSB first serialization. This is a compile-time option which needs to be set before IP generation.

  • 0 = LSB-first serialization
  • 1 = MSB-first serialization

Note: JESD204B converter device may support either MSB-first serialization or LSB-first serialization.

In order to support MSB-first serialization, both byte_reversal and bit_reversal needs to be set to 1 when generating the IP.

When bit_reversal = 1, the word aligner reverses the TX parallel data bits before transmitting it to the PMA for serialization.

For example; in 20-bit mode; D[19:0] is rewired to D[0:19] and in 40-bit mode; D[39:0] is rewired to D[0:39].

 RO compile-time specific
0 byte_reversal

Byte reversal for LSB/MSB first serialization. This is a compile-time option which needs to be set before IP generation.

  • 0 = LSB-first serialization

Byte order = {octet3, octet2, octet1, octet0}

  • 1 = MSB-first serialization

Byte order = {octet0, octet1, octet2, octet3}

Note: JESD204B converter device may support either MSB-first serialization or LSB-first serialization. In order to support MSB-first serialization, both byte_reversal and bit_reversal needs to be set to 1 when generating the IP.

When byte_reversal = 1, the byte order is reversed before transmitting data.

 RO compile-time specific
Table 24.  lane_ctrl_0Lane control and assignment for Lane 0.

Offset: 0x4
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9:2 rl0 Physical lane control reserve register RW 0x0
1 lane0_powerdown
Note:

This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 0.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane0_polarity

Set 1 to inverse Lane 0 Polarity.

When set, the TX interface inverts the polarity of the TX data. This register can be used to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals.

RW 0x0
Table 25.  lane_ctrl_1Lane control and assignment for Lane 1.

Offset: 0x8
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9:2 rl1 Physical lane control reserve register RW 0x0
1 lane1_powerdown
Note:

This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 1.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane1_polarity

Set 1 to inverse Lane 1 Polarity.

When set, the TX interface inverts the polarity of the TX data. This register can be used to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals.

RW 0x0
Table 26.  lane_ctrl_2Lane control and assignment for Lane 2.

Offset: 0xC
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9:2 rl2 Physical lane control reserve register RW 0x0
1 lane2_powerdown
Note:

This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 2.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane2_polarity

Set 1 to inverse Lane 2 Polarity.

When set, the TX interface inverts the polarity of the TX data. This register can be used to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals.

RW 0x0
Table 27.  lane_ctrl_3Lane control and assignment for Lane 3.

Offset: 0x10
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9:2 rl3 Physical lane control reserve register RW 0x0
1 lane3_powerdown
Note:

This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 3.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane3_polarity

Set 1 to inverse Lane 3 Polarity.

When set, the TX interface inverts the polarity of the TX data. This register can be used to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals.

RW 0x0
Table 28.  lane_ctrl_4Lane control and assignment for Lane 4.

Offset: 0x14
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9:2 rl4 Physical lane control reserve register RW 0x0
1 lane4_powerdown
Note:

This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 4.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane4_polarity

Set 1 to inverse Lane 4 Polarity.

When set, the TX interface inverts the polarity of the TX data. This register can be used to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals.

RW 0x0
Table 29.  lane_ctrl_5Lane control and assignment for Lane 5.

Offset: 0x18
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9:2 rl5 Physical lane control reserve register RW 0x0
1 lane5_powerdown
Note:

This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 5.

  • 0 = Normal mode
  • 1 = Power down

 RW 0x0
0 lane5_polarity

Set 1 to inverse Lane 5 Polarity.

When set, the TX interface inverts the polarity of the TX data. This register can be used to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals.

RW 0x0
Table 30.  lane_ctrl_6Lane control and assignment for Lane 6.

Offset: 0x1C
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9:2 rl6 Physical lane control reserve register RW 0x0
1 lane6_powerdown
Note:

This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 6.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane6_polarity

Set 1 to inverse Lane 6 Polarity.

When set, the TX interface inverts the polarity of the TX data. This register can be used to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals.

RW 0x0
Table 31.  lane_ctrl_7Lane control and assignment for Lane 7.

Offset: 0x20
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9:2 rl7 Physical lane control reserve register RW 0x0
1 lane7_powerdown
Note:

This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 7.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane7_polarity

Set 1 to inverse Lane 7 Polarity.

When set, the TX interface inverts the polarity of the TX data. This register can be used to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swapped the positive and negative signals.

RW 0x0
Table 32.  dll_ctrlData link layer (DLL) and TX control.

Offset: 0x50
Bit Name Description Attribute Reset
31:17 Reserved Reserved RV 0x0
16 rr5 DLL control reserve register 5 RW 0x0
15 rr4 DLL control reserve register 4 RW 0x0
14 rr3 DLL control reserve register 3 RW 0x0
13 rr2 DLL control reserve register 2 RW 0x0
12 rr1 DLL control reserve register 1 RW 0x0
11 reinit_rxsyncn_rise

Control CGS state exit behavior during link reinitialization through syncn_sysref_ctrl (0x54) link_reinit.

  • 0 = Exit CGS state without detected SYNC~ rise from DAC converter. (Default)

If this mode is entered, transmitter shall transmit at least four /K28.5/ symbols and exit CGS state at next LMFC boundary during link reinitialization.

  • 1 = Exit CGS state only when detected SYNC~ rise from DAC converter. If this mode is entered, transmitter shall stay at CGS state and transmit /K28.5/ symbols until detected SYNC~ rise then exit CGS state at next LMFC boundary during link re-initialization.
RW 0x0
10 test_ilas_loop

Write 1 to this register will force the state machine to stay in Initial Lane Alignment Sequence (ILAS) state indefinitely after entry. ILAS Configuration will be transmitted during the second ILAS multi-frame. The rest of the multi-frame will have the start-of-multiframe character (/R/) followed by dummy data and end-of-multiframe (/A/).

There are 2 modes of entry per JESD204B spec Chapter 5.3.3.8.2:

  • If this mode is entered when receiver initiates synchronization request, transmitter shall initiate CGS. Upon completion of CGS, transmitter shall repeatedly transmit ILAS.
  • If there is no synchronization request upon test entry, transmitter shall transmit at least four /K28.5/ symbols. At the LMFC boundary, the transmitter shall repeatedly transmit ILAS.
RW 0x0
9 char_repl_disable

Disable character replacement for debug purposes. When this bit is set, end-of-frame (/F/) and end-of-multiframe (/A/) character replacement will be disabled.

0 = Character replacement enabled (Default)

1 = Character replacement disabled. Used for debug purposes.

 RW 0x0
8:1 ilas_multiframe

The counter is binary value minus 1.

ILAS required by subclass 1 and 2 consists of exactly 4 multiframes. However, configurations with multiple subclass 0 DAC devices may require additional multiframes to achieve lane alignment. Therefore, the length of ILAS shall be programmable from 4 up to 256 multiframes. When illegal values like 0/1/2 is set, the IP core will still run as 4 multiframes.

Note: This counter value will take effect regardless of subclass setting. User is advised not to change this register for Subclass 1 and Subclass 2.
RW 0x3
0 lane_sync_en

Lane synchronization enable is required multi-lane alignment for a JESD204B link.

0 = Lane synchronization is disabled. ILAS will be bypassed. The character replacement of user data during end of multiframe will be considered as end of frame.

1 = Lane Synchronization Enabled (Default)

Note: For device that is classified as NMCDA-SL, lane synchronization can be disabled. This bit has to be set to 1 for all other devices.
RW 0x1
Table 33.  syncn_sysref_ctrlSYNC_N and SYSREF control. Controls event sequencing related to SYNC_N and SYSREF signals.

Offset: 0x54
Bit Name Description Attribute Reset
31:21 Reserved Reserved RV 0x0
20 cgs_bypass_sysref

This bit applies to Subclass 1 only. Enabling DLL states transition from Code Group Synchronization (CGS) to Initial Lane Alignment Sequence (ILAS) to bypass SYSREF single detect sampling.

By default, JESD204B IP core will remain in CGS state until SYSREF is sampled. Once sysref_singledet is cleared, then only the DLL state can transition from CGS to ILAS on the next LMFC tick. Write 1 to this register to allow the IP core to exit out of CGS state without ensuring that at least one rising edge of SYSREF was sampled.

Note: This is a debug mode, where user can bypass SYSREF sampling if only a quick link up is required. Setting this bit to 1 may cause race condition between SYSREF sampling and CGS exit.
RW 0x0
19:12 lmfc_offset

The Local Multiframe Clock(LMFC) offset is binary value minus 1.

Upon the detection of the rising edge of SYSREF in continuous mode or single detect mode, the LMFC counter will be reset to the value set in lmfc_offset. LMFC counter operates in link clock domain therefore the legal value is from 0 to ((FxK/4)-1). If an out-of-range value is set, the LMFC offset will be internally reset to 0.

Note: By default, the rising edge of SYSREF will reset the LMFC counter to 0. However, if the system design has large phase offset between the SYSREF sampled by the converter device and the FPGA, user can virtually shift the SYSREF edges by changing the LMFC offset reset value using this register.
RW 0x0
11:7 Reserved Reserved RV 0x0
6 rr4 SYNCN and SYSREF control reserve register 4 RW 0x0
5 rr3 SYNCN and SYSREF control reserve register 3 RW 0x0
4 rr2 SYNCN and SYSREF control reserve register 2 RW 0x0
3 rr1 SYNCN and SYSREF control reserve register 1 RW 0x0
2 sysref_singledet

This register enables LMFC realignment with a single sample of rising edge of SYSREF. The bit is auto-cleared by hardware once SYSREF is sampled. If you require SYSREF to be sampled again (due to link reset or reinitialization), you must set this bit again.

This register also has another critical function: JESD204B IP core will never exit out of CGS unless at least a SYSREF edge is sampled. This is to prevent race condition between SYSREF being sampled and the exit of CGS to ILAS. If CGS transition to ILAS before the common SYSREF is sampled for both the IP core and converter device, this would cause undeterministic latency as the ILAS is transmitted is based on the free running LMFC counter coming out of reset.

0 = Any rising edge of SYSREF will not reset the LMFC counter.

1 = Resets the LMFC counter on the first rising edge of SYSREF and then clears this bit. (Default)

Note: Intel recommends that you use sysref_singledet with sysref_alwayson even if you want to do SYSREF continuous detection mode. This is because this register can indicate whether SYSREF was ever sampled. This register also prevents race condition as mentioned above. Using only SYSREF single detect mode will not be able to detect incorrect SYSREF period.
RW1S 0x1
1 sysref_alwayson

This register enables LMFC realignment at every rising edge of SYSREF. LMFC counter is reset when every SYSREF transition from 0 to 1 is detected.

0 = Any rising edge of SYSREF will not reset the LMFC counter.

1 = Continuously resets LMFC counter at every SYSREF rising edge.

Note:

When this bit is set, the SYSREF period will be checked that it never violates internal local multiframe period and this period can only be n-integer multiplied of ((FxK)/4). If the SYSREF period is different from the local multiframe period, register tx_err (0x60) sysref_lmfc_err will be asserted and an interrupt will be triggered.

If you want to change SYSREF period, this bit should be set to 0 first. After SYSREF clock has stabilized, this bit is set to 1 to sample the rising edges of the new SYSREF.

RW 0x0
0 link_reinit

JESD204B IP core will reinitialize the link to enter Code Group Synchronization by transmitting /K28.5/.

The software will need to check that SYNC_N register tx_status0 (0x80) dev_syncn is 1 before setting this register.

(This bit automatically clears once link reinitialization is entered by hardware).

0 = No link reinit request (Default)

1 = Reinitialize the link.

 RW1S 0x0
Table 34.  ctrl_reserveControl Register Reserve

Offset: 0x58
Bit Name Description Attribute Reset
31:0 rc32 Reserved RW 0x0
Table 35.  tx_errThis register logs errors detected in the FPGA IP. Each set bit in the register will generate interrupt, if enabled by corresponding bits in the TX Error Enable (tx_err_enable (0x64)). After servicing the interrupt, the software must clear the appropriate serviced interrupt status bit and ensure that no other interrupts are pending.

Offset: 0x60
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9 efifo_overflow_err Assert when overflow happens on any of the lane’s TX EFIFO. RW1C 0x0
8 re4 TX Error Reserve Status 4 RW1C 0x0
7 src_tx_alarm Detected tx_alarm signal assertion from Tile SRC. Indicates a non-requested change in TX lane state (such as PLL lock lost), or other error condition. This event might be overlapping with pll_lock_err. RW1C 0x0
6 syspll_lock_err Detected system PLL unlock (from Tile) drop when JESD204B link is running. This can be derived from lane_current_state[2]=0 (from Tile SRC) RW1C 0x0
5 txpll_lock_err Detected 1 or more lanes of ux_all_synthlockstatus (from Tile) drop when JESD204B link is running. This means XCVR PLL is unexpectedly unlocked. RW1C 0x0
4 syncn_reinit_req

Receiver has requested reinitialization by asserting SYNC_N low for more than 5 frames and 9 octets.

Note: Upon the detection of SYNC_N link reinitialization request from the receiver, the JESD204B IP enters Code Group Synchronization (CGS) and transmits continuous /K28.5/. If you want to regenerate and sample SYSREF, enabling this interrupt notifies the software that the receiver has requested for link reinitialization.
RW1C 0x0
3 frame_data_invalid_err

This error bit is applicable only if you use Intel FPGA Transport Layer in your design. This error bit will be asserted if the upstream component de-asserts jesd204_tx_data_valid signal at the Intel FPGA Transport Layer AV-ST bus. The Transport Layer expects the upstream device in the system will always send the valid data with zero latency when jesd204_tx_data_ready is asserted by the Transport Layer.

Note: If this error detection is not required, the user can tie off the AV-ST signal jesd204_tx_frame_error to 0.
RW1C 0x0
2 dll_data_invalid_err

This error bit will be asserted if the TX detects data invalid on the AV-ST bus when data is requested. By design, the JESD204B TX IP core expects the upstream device (JESD204B Transport Layer) will always send the valid data with zero latency when jesd204_tx_data_ready is asserted.

Note: If this error detection is not required, the user can tie off the AV-ST signal jesd204_tx_link_valid to 1.
RW1C 0x0
1 sysref_lmfc_err When register syncn_sysref_ctrl (0x54) sysref_alwayson is set to 1, the LMFC counter will check whether SYSREF period matches the LMFC counter where it is n-integer multiplier of the (FxK/4). If SYSREF period does not match the LMFC period, this bit will be asserted. RW1C 0x0
0 syncn_err

The JESD204B receiver indicates error through the SYNC_N signal.

 RW1C 0x0
Table 36.  tx_err_enableThis register enables the error types that will generate interrupt. Setting 0 to the register bits will disable the specific error type from generating interrupt.

Offset: 0x64
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9 efifo_overflow_err_en EFIFO overflow error interrupt enable RW 0x1
8 re4_en TX Error Reserve 4 interrupt enable RW 0x1
7 src_tx_alarm_en SRC TX alarm interrupt enable RW 0x1
6 syspll_lock_err_en System PLL Lock error interrupt enable RW 0x1
5 txpll_lock_err_en TX XCVR PLL Lock error interrupt enable RW 0x1
4 syncn_reinit_req_en SYNCN reinit request interrupt enable RW 0x1
3 frame_data_invalid_err_en Transport layer frame data invalid error interrupt enable RW 0x1
2 dll_data_invalid_err_en Link data invalid error interrupt enable RW 0x1
1 sysref_lmfc_err_en SYSREF LMFC error interrupt enable RW 0x1
0 syncn_err_en SYNC_N error type interrupt enable RW 0x1
Table 37.  tx_status0Monitor ports of internal signals and counter which will be useful for debug.

Offset: 0x80

Note: The bits that are compile-time specific are not configurable through register. You must recompile to change the value.)
Bit Name Description Attribute Reset
31:21 Reserved Reserved RV 0x0
20:13 dbg_adjcnt

Number of adjustment resolution steps of DAC LMFC in device link clock resolution.

Applies to Subclass 2 only.

Note: For Subclass 2 operations, the JESD204B IP calculates the phase of the SYNC_N deassertion from the receiver with respect to internal LMFC counter. Interrupt will be triggered with either tx_err (0x60) syncn_err or

syncn_reinit_req set.

This register along with dbg_adjdir and dbg_phadj latch the phase offset, direction and resolution based on phase detection using link clock.

Hysteresis and device clock ratio calculation should be done in the software.

 ROV 0x0
12 dbg_adjdir

Adjustment direction of DAC LMFC to the nearest LMFC tick. Applies to Subclass 2 only.

0 = Advance

1 = Delay

Note: For Subclass 2 operations, the JESD204B IP calculates the phase of the SYNC_N deassertion from the receiver with respect to internal LMFC counter. Interrupt will be triggered with either tx_err (0x60) syncn_err or syncn_reinit_req set.

This register along with dbg_phadj and dbg_adjcnt latch the phase offset, direction and resolution based on phase detection using link clock.

Hysteresis and device clock ratio calculation should be done in the software.

 ROV 0x0
11 dbg_phadj

SYNC_N deassertion is not-in-phase with the internal LMFC counter.

Applies to Subclass 2 only.

0 = DAC LMFC is aligned to device LMFC.

1 = DAC LMFC is NOT aligned to device LMFC

Note: For Subclass 2 operations, the JESD204B IP calculates the phase of the SYNC_N deassertion from the receiver with respect to internal LMFC counter. Interrupt will be triggered with either tx_err (0x60) syncn_err or syncn_reinit_req set.

This register along with dbg_adjdir and dbg_adjcnt latch the phase offset, direction and resolution based on phase detection using link clock.

Hysteresis and device clock ratio calculation should be done in the software.

 ROV 0x0
10:3 ilas_cnt This is a binary minus 1 value. The counter value reflects on which number of ILAS multiframe the DLL state machine is in. ROV 0x0
2:1 dll_state

Current state of Data Link Layer (DLL).

00 = Code Group Synchronization (CGS)

01 = Initial Lane Alignment Sequence (ILAS)

10 = User Data Mode

11 = D21.5 test mode

 ROV 0x0
0 dev_syncn

Internal SYNC_N value.

0 = Receiver is asserting synchronization request.

1 = JESD204B link is out of synchronization.

 ROV 0x0
Table 38.  tx_status1Monitor ports of internal signals and counter which will be useful for debug.

Offset: 0x84
Bit Name Description Attribute Reset
31 lane7_tx_desired_state SIP Reset Sequencer control for lane7 ROV 0x0
30:28 lane7_tx_current_state[2:0] Tile SRC status for lane7 ROV 0x0
27 lane6_tx_desired_state SIP Reset Sequencer control for lane6 ROV 0x0
26:24 lane6_tx_current_state[2:0] Tile SRC status for lane6 ROV 0x0
23 lane5_tx_desired_state SIP Reset Sequencer control for lane5 ROV 0x0
22:20 lane5_tx_current_state[2:0] Tile SRC status for lane5 ROV 0x0
19 lane4_tx_desired_state SIP Reset Sequencer control for lane4 ROV 0x0
18:16 lane4_tx_current_state[2:0] Tile SRC status for lane4 ROV 0x0
15 lane3_tx_desired_state SIP Reset Sequencer control for lane3 ROV 0x0
14:12 lane3_tx_current_state[2:0] Tile SRC status for lane3 ROV 0x0
11 lane2_tx_desired_state SIP Reset Sequencer control for lane2 ROV 0x0
10:8 lane2_tx_current_state[2:0] Tile SRC status for lane2 ROV 0x0
7 lane1_tx_desired_state SIP Reset Sequencer control for lane1 ROV 0x0
6:4 lane1_tx_current_state[2:0] Tile SRC status for lane1 ROV 0x0
3 lane0_tx_desired_state SIP Reset Sequencer control for lane0 ROV 0x0
2:0 lane0_tx_current_state[2:0] Tile SRC status for lane0 ROV 0x0
Table 39.  tx_status2Monitor ports of internal signals and counter which will be useful for debug.

Offset: 0x88
Bit Name Description Attribute Reset
31:24 Reserved Reserved RV 0x0
23 lane7_pll_locked Tile PLL status for lane 7, indicates PLL is locked. ROV 0x0
22 lane6_pll_locked Tile PLL status for lane 6, indicates PLL is locked. ROV 0x0
21 lane5_pll_locked Tile PLL status for lane 5, indicates PLL is locked. ROV 0x0
20 lane4_pll_locked Tile PLL status for lane 4, indicates PLL is locked. ROV 0x0
19 lane3_pll_locked Tile PLL status for lane 3, indicates PLL is locked. ROV 0x0
18 lane2_pll_locked Tile PLL status for lane 2, indicates PLL is locked. ROV 0x0
17 lane1_pll_locked Tile PLL status for lane 1, indicates PLL is locked. ROV 0x0
16 lane0_pll_locked Tile PLL status for lane 0, indicates PLL is locked. ROV 0x0
15:8 Reserved Reserved RV 0x0
7 rs28 Reserved status 8. ROV 0x0
6 rs27 Reserved status 7. ROV 0x0
5 rs26 Reserved status 6. ROV 0x0
4 rs25 Reserved status 5. ROV 0x0
3 rs24 Reserved status 4. ROV 0x0
2 rs23 Reserved status 3. ROV 0x0
1 rs22 Reserved status 2. ROV 0x0
0 rs21 Reserved status 1. ROV 0x0
Table 40.  tx_status3TX status reserve.

Offset: 0x8C
Bit Name Description Attribute Reset
31:0 rs32 TX status reserve. ROV 0x0
Table 41.  ilas_data0Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0x90
Name Description Attribute Reset
Reserved Reserved RV 0x0
bid Bank Identification value transmitted during ILAS RO compile-time specific
did Device Identification value transmitted during ILAS RO compile-time specific
Table 42.  ilas_data1Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0x94
Bit Name Description Attribute Reset
31:24 M

Number of converters per device. 0-based value. I.e 0=1 converter, 1=2 converters.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
23:21 Reserved Reserved RV 0x0
20:16 K

Link K.

Number of frames per multiframe. 0-based value. I.e 0=1 converter, 1=2 converters.

A multiframe is defined as a group of K successive frames where K is between 1 and 32 and such that the number of octets per multiframe is between 17 and 1024. The IP requires that FxK must be divisible by 4.

RO compile-time specific
15:8 F

Number of octets per frame. 0-based value. I.e 0=1 octet, 1=2 octets.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
7 scr_en

Enable or disable descrambler.

0 = Disable descrambler

1 = Enable descrambler

 RO compile-time specific
6:5 Reserved Reserved RV 0x0
4:0 L

Number of lanes per link. 0-based value. I.e 0=1 lane, 1=2 lanes.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
Table 43.  ilas_data2Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0x98
Name Description Attribute Reset
HD High Density format. RO compile-time specific
Reserved Reserved RV 0x0
CF

Number of control words per frame clock per link. 1-based value. I.e 0=0 word, 1=1 word.

  • CF = L is encoded as: control words on all lanes
  • CF = 31 can only occur when L = 31
 RO compile-time specific
jesdv

JESD204x version.

  • 000 = JESD204A
  • 001 = JESD204B
 RO 0x1
S

Number of samples per converter frame cycle. 0-based value. I.e 0=1 sample, 1=2 samples.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
subclassv

Device Subclass Version

b000: Subclass 0

b001: Subclass 1

b010: Subclass 2

 RO compile-time specific
NP

Number of bits per converter sample. 0-based value. I.e 0=1 bit, 1=2 bits.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
CS Number of control bits per converter sample. 1-based value. I.e 0=0 bit, 1=1 bit. RO compile-time specific
Reserved Reserved RV 0x0
N

Converter resolution. 0-based value. I.e 0=1 bit, 1=2 bits.

Note that CSR indexing is different from the parameter indexing. If parameter=`d8, this register field will be `d7.

 RO compile-time specific
Table 44.  ilas_data3Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0x9C
Bit Name Description Attribute Reset
31 phadj

Phase adjustment request of DAC LMFC. The register is auto-cleared by the hardware after sending ILAS 2nd multiframe.

Applies to Subclass 2 only.

RW

(hardware clear (hwclr))

 Compile-time specific
30 adjdir

Adjustment direction of DAC LMFC. The register is auto-cleared by the hardware after sending ILAS 2nd multiframe.

Applies to Subclass 2 only.

0 = Advance

1 = Delay

 RW (hardware clear (hwclr)) Compile-time specific
29:20 Reserved Reserved RV 0x0
19:16 adjcnt

No of adjustment resolution steps of DAC LMFC. The register is autocleared by hardware after sending ILAS 2nd multiframe.

Applies to Subclass 2 only

 RW (hardware clear (hwclr)) Compile-time specific
15:8 rsvd2 ILAS reserved 2 bytes RW 0x0
7:0 rsvd1 ILAS reserved 1 bytes RW 0x0
Table 45.  ilas_data4Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0xA0
Bit Name Description Attribute Reset
31:29 Reserved Reserved RV 0x0
28:24 lid_l3 Lane Identification for lane 3 transmitted during ILAS. RO compile-time specific
23:21 Reserved Reserved RV 0x0
20:16 lid_l2 Lane Identification for lane 2 transmitted during ILAS. RO compile-time specific
15:13 Reserved Reserved RV 0x0
12:8 lid_l1 Lane Identification for lane 1 transmitted during ILAS. RO compile-time specific
7:5 Reserved Reserved RV 0x0
4:0 lid_l0 Lane Identification for lane 0 transmitted during ILAS. RO compile-time specific
Table 46.  ilas_data5Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0xA4
Bit Name Description Attribute Reset
31:29 Reserved Reserved RV 0x0
28:24 lid_l7 Lane Identification for lane 7 transmitted during ILAS. RO compile-time specific
23:21 Reserved Reserved RV 0x0
20:16 lid_l6 Lane Identification for lane 6 transmitted during ILAS. RO compile-time specific
15:13 Reserved Reserved RV 0x0
12:8 lid_l5 Lane Identification for lane 5 transmitted during ILAS. RO compile-time specific
7:5 Reserved Reserved RV 0x0
4:0 lid_l4 Lane Identification for lane 4 transmitted during ILAS. RO Compile-time specific
Table 47.  ilas_data8Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0xB0
Bit Name Description Attribute Reset
31:24 fchk_l3 ILAS checksum lane 3. Checksum is the modulo 256 of parameters listed ILAS configuration data. RW Compile-time specific
23:16 fchk_l2 ILAS checksum lane 2. Checksum is the modulo 256 of parameters listed ILAS configuration data. RW Compile-time specific
15:8 fchk_l1 ILAS checksum lane 1. Checksum is the modulo 256 of parameters listed ILAS configuration data. RW Compile-time specific
7:0 fchk_l0 ILAS checksum lane 0. Checksum is the modulo 256 of parameters listed ILAS configuration data. RW Compile-time specific
Table 48.  ilas_data9Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0xB4
Bit Name Description Attribute Reset
31:24 fchk_l7 ILAS checksum lane 7. Checksum is the modulo 256 of parameters listed ILAS configuration data. RW Compile-time specific
23:16 fchk_l6 ILAS checksum lane 6. Checksum is the modulo 256 of parameters listed ILAS configuration data. RW Compile-time specific
15:8 fchk_l5 ILAS checksum lane 5. Checksum is the modulo 256 of parameters listed ILAS configuration data. RW Compile-time specific
7:0 fchk_l4 ILAS checksum lane 4. Checksum is the modulo 256 of parameters listed ILAS configuration data. RW Compile-time specific
Table 49.  ilas_data12Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0xC0
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9:2 fxk_h

Upper bits of FxK[8:2]. This is a binary value minus 1.

Link F multiply with Link K must be divisible by 4.

Note: The IP runs on 32-bit data width boundary per channel, so you must always ensure that FxK must be divisible by 4.

 RO Compile-time specific
1:0 fxk_l

Lower bits of FxK[1:0]. This is a binary value minus 1.

Link F multiply with Link K must be divisible by 4.

Note: The IP runs on 32-bit data width boundary per channel, so you must always ensure that FxK must be divisible by 4. FxK (in binary value minus 1) always results to a value of 2'b11in the lower 2 bits.

RO 0x3
Table 50.  tx_testJESD204 test control.

Offset: 0xD0
Bit Name Description Attribute Reset
31:4 Reserved Reserved RV 0x0
3:0 tx_testmode

b0xxx is reserved for the JESD204B IP and 'b1xxx is reserved for external components out of the JESD204B IP.

JESD204B IP test mode:

  • 0000 = No test (Default)
  • 0001 = K28.5
  • 0010 = D21.5

JESD204B IP reference design test mode:

  • 1000 = Alternating Checkerboard
  • 1001 = Ramp
  • 1010 = PRBS
 RW 0x0
Table 51.  user_test_pattern_aTest pattern per sample per converter.

Offset: 0xD4
Bit Name Description Attribute Reset
31:16 test_pattern1 User test pattern 1. RW 0x0
15:0 test_pattern0 User test pattern 0. RW 0x0
Table 52.  user_test_pattern_bTest pattern per sample per converter.

Offset: 0xD8
Bit Name Description Attribute Reset
31:16 test_pattern3 User test pattern 3. RW 0x0
15:0 test_pattern2 User test pattern 2. RW 0x0
Table 53.  user_test_pattern_cTest pattern per sample per converter.

Offset: 0xDC
Bit Name Description Attribute Reset
31:16 test_pattern5 User test pattern 5. RW 0x0
15:0 test_pattern4 User test pattern 4. RW 0x0
Table 54.  user_test_pattern_dTest pattern per sample per converter.

Offset: 0xE0
Bit Name Description Attribute Reset
31:16 test_pattern7 User test pattern 7. RW 0x0
15:0 test_pattern6 User test pattern 6. RW 0x0
Table 55.  tx_unusedUnused.

Offset: 0x3FC
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Level Two Title