F-Tile JESD204B Intel® FPGA IP User Guide

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ID 723907
Date 5/18/2022
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Document Table of Contents
Document Table of Contents x
1. F-Tile JESD204B IP Quick Reference 2. About the F-Tile JESD204B Intel® FPGA IP 3. Getting Started 4. F-Tile JESD204B IP Functional Description 5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines 6. F-Tile JESD204B IP Debug Guidelines 7. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide
2. About the F-Tile JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. F-Tile JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. F-Tile JESD204B IP Design Considerations 3.8. F-Tile JESD204B Intel® FPGA IP Parameters 3.9. F-Tile JESD204B IP Component Files
3.6. Design Walkthrough x
3.6.1. Creating a New Intel® Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the F-Tile JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.7. F-Tile JESD204B IP Design Considerations x
3.7.1. Integrating the F-Tile JESD204B IP in Platform Designer 3.7.2. Pin Assignments 3.7.3. Adding External System PLL
4. F-Tile JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. System PLL Clock
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Register Map and Definition 4.7.3. Transmitter Registers 4.7.4. Receiver Registers
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. F-Tile JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. F-Tile JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment
1. F-Tile JESD204B IP Quick Reference
2. About the F-Tile JESD204B Intel® FPGA IP
3. Getting Started
4. F-Tile JESD204B IP Functional Description
5. F-Tile JESD204B IP Deterministic Latency Implementation Guidelines
6. F-Tile JESD204B IP Debug Guidelines
7. Document Revision History for the F-Tile JESD204B Intel® FPGA IP User Guide

4.7.4. Receiver Registers

Table 56.  Address Table for JESD204 RX Registers
Address Title
0x0 Physical Lane Control Common
0x4 Physical Lane Control 0
0x8 Physical Lane Control 1
0xC Physical Lane Control 2
0x10 Physical Lane Control 3
0x14 Physical Lane Control 4
0x18 Physical Lane Control 5
0x1C Physical Lane Control 6
0x20 Physical Lane Control 7[CACY1]
0x24 - 0x4F -
0x50 Data Link Layer (DLL) and RX Control
0x54 SYNCN and SYSREF Control[CACY2]
0x58 Reserved Control
0x5C - 0x5F -
0x60 JESD204 RX Error Status 0
0x64 JESD204 RX Error Status 1
0x68-0x73[CACY3] -
0x74 JESD204 RX Error Interrupt Enable
0x78 JESD204 RX Error Link Reinitialization Enable
0x7C - 0x7F -
0x80 JESD204 RX Status 0
0x84 JESD204 RX Status 1
0x88 JESD204 RX Status 2
0x8C JESD204 RX Status 3
0x90 – 0x93 -
0x94 JESD204 RX ILAS data 1
0x98 JESD204 RX ILAS data 2
0x9C – 0x9F -
0xA0 JESD204 RX ILAS octet 0
0xA4 JESD204 RX ILAS octet 1
0xA8 JESD204 RX ILAS octet 2
0xAC JESD204 RX ILAS octet 3
0xB0 – 0xBF -
0xC0 JESD204 RX ILAS data 12
0xC4 – 0xCF -
0xD0 JESD204 RX test control
0xD4 – 0xEF -
0xF0 JESD204 RX Status 4
0xF4 JESD204 RX Status 5
0xF8 JESD204 RX Status 6
0xFC JESD204 RX Status 7
0x100-0x3F8 -
0x3FC Unused
Table 57.  lane_ctrl_commonCommon lane control and assignment. The common lane control applies to all lanes in the link.

Offset: 0x0

Note: The bits that are compile-time specific are not configurable through register. You must recompile to change the value.)
Bit Name Description Attribute Reset
31:3 Reserved Reserved RV 0x0
2 rl Physical lane control reserve register RW 0x0
1 bit_reversal

Bit reversal for LSB/MSB first serialization. This is a compile-time option which needs to be set before IP generation.

  • 0 = LSB-first serialization
  • 1 = MSB-first serialization
Note: JESD204B converter device may support either MSB-first serialization or LSB-first serialization.

To support MSB-first serialization, you must set both byte_reversal and bit_reversal bits to 1 when generating the IP.

When bit_reversal = 1, the word aligner reverses the RX parallel data bits upon receiving the PMA deserialized data.

For example; in 20-bit mode; D[19:0] is rewired to D[0:19] and in 40-bit mode; D[39:0] is rewired to D[0:39].

 RO Compile-time specific
0 byte_reversal

Byte reversal for LSB/MSB first serialization. This is a compile-time option which needs to be set before IP generation.

  • 0 = LSB-first serialization

Byte order = {octet3, octet2, octet1, octet0}

  • 1 = MSB-first serialization

Byte order = {octet0, octet1, octet2, octet3}

Note: JESD204B converter device may support either MSB-first serialization or LSB-first serialization.

To support MSB-first serialization, both byte_reversal and bit_reversal needs to be set to 1 when generating the IP.

When byte_reversal = 1, the word aligner reverses the byte order.

 RO Compile-time specific
Table 58.  lane_ctrl_0Lane control and assignment for lane 0.

Offset: 0x4
Bit Name Description Attribute Reset
31:3 Reserved Reserved RV 0x0
2 alllanes_patternalign_en

Enables word alignment to the specified pattern boundary alignment during link initialization. You should set this bit to 1 in normal operations.

Note: You can disable this bit to debug bit slip error.

 RW 0x1
1 lane0_powerdown
Note:

This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 0.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane0_polarity

Set 1 to inverse lane 0 polarity.

When set, the RX interface inverts the polarity of the RX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals.

RW 0x0
Table 59.  lane_ctrl_1Lane control and assignment for lane 1.

Offset: 0x8
Bit Name Description Attribute Reset
31:3 Reserved Reserved RV 0x0
2 rl1 Physical lane control reserve register. RW 0x1
1 lane1_powerdown
Note:

This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 1.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane1_polarity

Set 1 to inverse lane 1 polarity.

When set, the RX interface inverts the polarity of the RX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals.

RW 0x0
Table 60.  lane_ctrl_2Lane control and assignment for lane 2.

Offset: 0xC
Bit Name Description Attribute Reset
31:3 Reserved Reserved RV 0x0
2 rl2 Physical lane control reserve register. RW 0x1
1 lane2_powerdown
Note:

Note: This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 2.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane2_polarity

Set 1 to inverse lane 2 polarity.

When set, the RX interface inverts the polarity of the RX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals.

RW 0x0
Table 61.  lane_ctrl_3Lane control and assignment for lane 3.

Offset: 0x10
Bit Name Description Attribute Reset
31:3 Reserved Reserved RV 0x0
2 rl3 Physical lane control reserve register. RW 0x1
1 lane3_powerdown
Note:

Note: This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 3.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane3_polarity

Set 1 to inverse lane 3 polarity.

When set, the RX interface inverts the polarity of the RX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals.

RW 0x0
Table 62.  lane_ctrl_4Lane control and assignment for lane 4.

Offset: 0x14
Bit Name Description Attribute Reset
31:3 Reserved Reserved RV 0x0
2 rl4 Physical lane control reserve register. RW 0x1
1 lane4_powerdown
Note:

Note: This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 4.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane4_polarity

Set 1 to inverse lane 4 polarity.

When set, the RX interface inverts the polarity of the RX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals.

RW 0x0
Table 63.  lane_ctrl_5Lane control and assignment for lane 5.

Offset: 0x18
Bit Name Description Attribute Reset
31:3 Reserved Reserved RV 0x0
2 rl5 Physical lane control reserve register. RW 0x1
1 lane5_powerdown
Note:

Note: This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 5.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane5_polarity

Set 1 to inverse lane 5 polarity.

When set, the RX interface inverts the polarity of the RX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals.

RW 0x0
Table 64.  lane_ctrl_6Lane control and assignment for lane 6.

Offset: 0x1C
Bit Name Description Attribute Reset
31:3 Reserved Reserved RV 0x0
2 rl6 Physical lane control reserve register. RW 0x1
1 lane6_powerdown
Note:

Note: This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 6.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
0 lane6_polarity

Set 1 to inverse lane 6 polarity.

When set, the RX interface inverts the polarity of the RX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals.

RW 0x0
Table 65.  lane_ctrl_7Lane control and assignment for lane 7.

Offset: 0x20
Name Description Attribute Reset
Reserved Reserved RV 0x0
rl7 Physical lane control reserve register. RW 0x1
lane7_powerdown
Note:

Note: This reserved register is unused in F-Tile JESD204B IP.

Power down control for lane 7.

  • 0 = Normal mode
  • 1 = Power down
 RW 0x0
lane7_polarity

Set 1 to inverse lane 7 polarity.

When set, the RX interface inverts the polarity of the RX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals.

RW 0x0
Table 66.  dll_ctrlData link layer (DLL) and RX control.

Offset: 0x50
Bit Name Description Attribute Reset
31:17 Reserved Reserved RV 0x0
16 rd4 DLL control reserve register 4. RW 0x0
15 rd3 DLL control reserve register 3. RW 0x0
14 rd2 DLL control reserve register 2. RW 0x0
13 rd1 DLL control reserve register 1. RW 0x0
12 link_reinit_disable

Disable link reinitialization for all error conditions except for Code Group error. This is a global link reinitialization disable that overrides register rx_err_link_reinit (0x78).

  • 0 = Enable link reinitialization during error condition (Default)
  • 1 = Disable link reinitialization for all error conditions except for Code Group Error.
 RW 0x0
11 rs0 DLL control reserve register 0. RW 0x0
10:7 ilas_data_sel

JESD204B link configuration data transmitted during the 2nd ILAS multiframe is latched per lane.

This register is used to select desired lane's link configuration data to be routed to the ilas_octet0 (0xa0), ilas_octet1 (0xa4), ilas_octet2 (0xa8), and ilas octet3 (0xac) registers. The link configuration data in ilas_octet0 to ilas_octet3 will be invalid (all zeros) if invalid lane is selected.

4'b0000 = lane 0 ILAS link configuration data, 4'b0001 = lane 1 ILAS link configuration data, ...

4'b0111 = lane 7 ILAS link configuration data.

 RW 0x0
6:3 Reserved Reserved RV 0x0
2 dis_lane_align_det

In normal operation, the JESD204B IP is required to detect end-of-multiframe /A/ character and checks for lane alignment. You can disable this check for debug purposes.

  • 0 = Enable lane alignment detection (Default)
  • 1 = Disable lane alignment detection
 RW 0x0
1 dis_frame_align_det

In normal operation, JESD204B IP is required to detect end-of-frame /F/ character and checks for frame alignment. You can disable this check for debug purposes.

  • 0 = Enable frame alignment detection (Default)
  • 1 = Disable frame alignment detection
 RW 0x0
0 lane_sync_en

Lane synchronization enable is required multilane alignment for a JESD204B link.

0 = Disable lane synchronization is disabled.

The IP expects the transmit device to bypass ILAS, and the DLL state transition from CGS to USER DATA and checks for this transition to release the data from the elastic buffer.

1 = Enable lane synchronization (Default).

The IP expects the DLL state from the transmit device to transition from CGS to ILAS then to USER DATA and checks from ILAS.

Note: For device that is classified as NMCDA-SL, lane synchronization can be disabled. This bit must be set to 1 for all other devices.
RW 0x1
Table 67.  syncn_sysref_ctrlSYSREF control.

Offset: 0x54

Note: The bits that are compile-time specific are not configurable through register. You must recompile to change the value.)
Bit Name Description Attribute Reset
31:25 Reserved Reserved RV 0x0
24:21 syncn_delay

This 4-bit register extends SYNC_N assertion (low state) by delaying the deassertion. The legal value is 0 to 15; with 0 indicating no additional delay on SYNC_N deassertion.

For Subclass 0, the value indicates the number of link clocks SYNC_N will be extended.

For Subclass 1 and 2, the value indicates the number of multi-frames SYNC_N will be extended.

 RW 0x00
20 cgs_bypass_sysref

This bit applies to Subclass 1 only. Enabling DLL states transition from Code Group Synchronization (CGS) to Initial Lane Alignment Sequence (ILAS) to bypass SYSREF single detect sampling.

By default, the JESD204B IP remains in CGS state (asserting SYNC_N) until SYSREF is sampled. Once sysref_singledet is cleared, then only the DLL state can transition from CGS to ILAS on the next LMFC tick.

Write 1 to this register to allow the IP to exit out of CGS state without ensuring that at least one rising edge of SYSREF was sampled.

Note: This is a debug mode, where you can bypass SYSREF sampling if only a quick link up is required. Setting this bit to 1 may cause race condition between SYSREF sampling and CGS exit.
RW 0x0
19:12 lmfc_offset

The LMFC offset is binary value minus 1. Upon the detection of the rising edge of SYSREF in continuous mode or single detect mode, the LMFC counter resets to the value set in lmfc_offset.

LMFC counter operates in link clock domain, therefore the legal value for the counter is from 0 to ((FxK/4)-1). If an out-of-range value is set, the LMFC offset internally resets to 0.

By default, the rising edge of SYSREF will reset the LMFC counter to 0. However, if the system design has large phase offset between the SYSREF sampled by the converter device and the FPGA, you can virtually shift the SYSREF edges by changing the LMFC offset reset value using this register.

RW 0x00
11:3 rbd_offset

This is a binary minus 1 value. RX Buffer Delay (RBD) offset. RX elastic buffer will align the data from multiple lanes of the link and release the buffer at the LMFC boundary (rbd_offset = 0).

This register provides flexibility for an early RBD release opportunity. Legal value of RBD offset is from ((FxK/4)-1) down to 0 as it is aligned in number of link clocks. If rbd_offset is set out of the legal value, the RBD elastic buffer will be immediately released.

Note: In Subclass 1, the earliest lane data right up to the latest lane data will be stored in the elastic buffer. The data is deskewed and release at the LMFC boundary where (rbd_offset = 0). The position of the latest lane arrival with respect to the LMFC internal counter will be reported in register rx_status0 (0x80) rbd_count. Set a safe RBD release in this register to ensure deterministic latency in power cycle mode. Refer to the application note on deterministic latency for more information.
RW 0x0
2 sysref_singledet

This register enables LMFC realignment with a single sample of rising edge of SYSREF. The bit is auto-cleared by hardware once SYSREF is sampled. If you require SYSREF to be sampled again (due to link reset or reinitialization), you must set this bit again.

This register also has another critical function. The JESD204B IP never exits out of CGS unless at least a SYSREF edge is sampled. This is to prevent race condition between SYSREF being sampled and the exit of CGS to ILAS. If CGS transitions to ILAS before the common SYSREF is sampled for both the IP and converter device, this would cause undeterministic latency as the ILAS is transmitted based on the free running LMFC counter coming out of reset.

  • 0 = Any rising edge of SYSREF will not reset the LMFC counter.
  • 1 = Resets the LMFC counter on the first rising edge of SYSREF and then clears this bit. (Default)

Intel recommends to use sysref_singledet with sysref_alwayson even if you want to do SYSREF continuous detection mode. This is because this register is able to indicate whether SYSREF was ever sampled. This register also prevents race condition as mentioned above. Using only SYSREF single detect mode will not be able to detect incorrect SYSREF period.

RW1S 0x1
1 sysref_alwayson

This register enables LMFC realignment at every rising edge of SYSREF. LMFC counter is reset when every SYSREF transition from 0 to 1 is detected.

0 = Any rising edge of SYSREF will not reset the LMFC counter.

1 = Continuously resets LMFC counter at every SYSREF rising edge.

Note: When this bit is set, the SYSREF period will be checked to make sure it never violates internal extended multiblock period and this period can only be n-integer multiplied of ((FxK)/4).

If the SYSREF period is different from the local extended multiblock period, register rx_err (0x60) sysref_lmfc_err will be asserted and an interrupt will be triggered.

If you want to change SYSREF period, this bit should be set to 0 first. After SYSREF clock has stabilized, this bit is set to 1 to sample the rising edges of the new SYSREF.

RW 0x0
0 link_reinit

The JESD204B IP will reinitialize the link to enter Code Group Synchronization by driving SYNC_N signal to 0. The software must check that SYNC_N (register rx_status0 (0x80) dev_syncn) is 1 before setting this register. (This bit will be automatically cleared once link reinitialization is entered by hardware).

  • 0 = No link reinit request (Default)
  • 1 = Reinitialize the link.
 RW1S 0x0
Table 68.  ctrl_reserveControl register reserve.

Offset: 0x58
Bit Name Description Attribute Reset
31:0 Reserved Reserved RW 0x0
Table 69.  rx_err0This register logs errors detected in the FPGA IP. Errors detected in the JESD204B IP will be logged in this register and rx_err1 (0x64). Each set bit in the register will generate interrupt, if enabled by corresponding bits in the RX Error Enable (rx_err_enable (0x74)). After servicing the interrupt, the software must clear the appropriate serviced interrupt status bit and ensure that no other interrupts are pending. Each set bit in the register issues link reinitialization, if enabled by corresponding bits in the RX Error Link Reinitialization Enable (rx_err_link_reinit (0x78)). Only Code Group error cannot be disabled and must always force link reinitialization in order to comply to the JESD204B specification.

Offset: 0x60
Bit Name Description Attribute Reset
31:11 Reserved Reserved RV 0x0
10 src_rx_alarm Detected rx_alarm signal assertion from Tile SRC. Indicates a non-requested change in RX lane state (such as CDR lock lost), or other error condition. This event might be overlapping with pll_lock_err. RW1C 0x0
9 syspll_lock_err Detected system PLL unlock (from Tile) drop when JESD204B link is running. This can be derived from lane_current_state[2]=0 (from Tile SRC) RW1C 0x0
8 rs4 RX error reserve status 4 RW1C 0x0
7 efifo_underflow_err

Detected 1 or more lanes of System clock Elastic FIFO is empty unexpectedly when the JESD204B link is running.

Note: You MUST reset the JESD204B link if this bit is triggered. The transceiver channel, and the JESD204B IP link reset must be applied.
RW1C 0x0
6 efifo_overflow_err

Detected 1 or more lanes of System clock Elastic FIFO is full unexpectedly when the JESD204B link is running.

Note: You MUST reset the JESD204B link if this bit is triggered. The transceiver channel, and the JESD204B IP link reset must be applied.
RW1C 0x0
5 rx_locked_to_data_err Detected 1 or more lanes of CDR locked loose lock when JESD204B link is running. RW1C 0x0
4 lane_deskew_err Asserted when lane to lane deskew exceed the LMFC boundary. This error will trigger when rbd_offset is not correctly programmed or the lane-to-lane skew within the device or across multi-device has exceeded the LMFC boundary. All ILA for all lanes should within one LMFC boundary. Refer to the application note on deterministic latency for more information. RW1C 0x0
3 frame_data_ready_err

This error bit will be asserted if the RX detects data ready by the upstream component is 0 on the AV-ST bus when data is valid. The Transport Layer expects the upstream device in the system (AV-ST sink component) will always be ready to receive the valid data from the Transport Layer.

Note: If this error detection is not required, the user can tie off the jesd204_rx_data_ready signal from the upstream to 1. This is the error from the transport layer instead from the JESD204B RX core.
RW1C 0x0
2 dll_data_ready_err

This error bit will be asserted if the RX detects data ready by the upstream component is 0 on the AV-ST bus when data is valid. By design, the JESD204B RX IP core expects the upstream device (JESD204B Transport Layer) will always be ready to receive the valid data from JESD204B RX IP core.

Note: If this error detection is not required, the user can tie off the AV-ST signal jesd204_rx_link_ready to 1.
RW1C 0x0
1 sysref_lmfc_err When register sysref_ctrl (0x54) sysref_alwayson is set to 1, the LMFC counter will check whether SYSREF period matches the LMFC counter where it is n-integer multiplier of the (FxK/4). If SYSREF period does not match the LMFC period, this bit will be asserted. RW1C 0x0
0 Reserved Reserved RV 0x0
Table 70.  rx_err1This register logs errors detected in the FPGA IP. Errors detected in the F-Tile JESD204B IP will be logged in this register and rx_err1 (0x64). Each set bit in the register will generate interrupt, if enabled by corresponding bits in the RX Error Enable (rx_err_enable (0x74)). After servicing the interrupt, the software must clear the appropriate serviced interrupt status bit and ensure that no other interrupts are pending. Each set bit in the register issues link reinitialization, if enabled by corresponding bits in the RX Error Link Reinitialization Enable (rx_err_link_reinit (0x78)). Only Code Group error cannot be disabled and must always force link reinitialization in order to comply to the F-Tile JESD204B specification..

Offset: 0x64
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9 ecc_fatal_err Assert when ECC fatal error occurs. This reflects a double bit error detected and uncorrected. RW1C 0x0
8 ecc_corrected_err Assert when ECC error has been corrected. This reflects a single bit error detected and corrected. RW1C 0x0
7 dllerrs_rs DLL error reserve status. RW1C 0x0
6 ilas_err

Indicates that there is missing ILAS sequence. The RX core expects ILAS sequence to be transmitted after /K28.5/ transmission. When /K28.5/ transmission is not followed by ILAS, this error will be triggered.

For devices NMCDA-SL where there is an option to disable transmission of ILAS, you need to mask out this error using error mask.

RW1C 0x0
5 disparity_err Running disparity error for all lanes, the received code group exists in the 8b10b decoding table but is not found in the proper column according to the current running disparity. RW1C 0x0
4 not_in_table_err Not in table error for all lanes, the received code group is not found in the 8b10b decoding table for either disparity. RW1C 0x0
3 unexpected_kchar

Unexpected control character error for all lanes, a control character is received that is not expected at the given character position.

Unexpected /A/ or /F/ character will be flagged as frame alignment error or lane alignment error.

 RW1C 0x0
2 lane_alignment_err

Lane alignment error for all lanes, the previous conversion samples may be in error. End-of-multiframe marker (/A/) position has misaligned.

Dynamic realignment is not supported

.

 RW1C 0x0
1 frame_alignment_err

Frame alignment error for all lanes, the previous conversion samples may be in error. End-of-frame marker (/F/ or /A/) position has misaligned.

Dynamic realignment is not supported.

 RW1C 0x0
0 cg_sync_err Code group synchronization error for all lanes, indicates that the state machine has returned to the CS_INIT state. RW1C 0x0
Table 71.  rx_err_enableThis register enables the error types that will generate interrupt. Setting 0 to the register bits will disable the specific error type from generating interrupt.

Offset: 0x74
Bit Name Description Attribute Reset
31:21 Reserved Reserved RV 0x0
20 ecc_fatal_err_en Enable interrupt for ECC fatal error type. Applicable to all lanes. RW 0x1
19 ecc_corrected_err_en Enable interrupt for ECC correctable error type. Applicable to all lanes. RW 0x0
18 dllerr_rs_en DLL error 1 enable reserve. Applicable to all lanes. RW 0x1
17 ilas_err_en Enable interrupt for missing ILAS error type. Applicable to all lanes. RW 0x1
16 disparity_err_en Enable interrupt for disparity error type. Applicable to all lanes. RW 0x1
15 not_in_table_err_en Enable interrupt for not in table error type. Applicable to all lanes. RW 0x1
14 unexpected_kchar_en Enable interrupt for unexpected control character type. Applicable to all lanes. RW 0x1
13 lane_alignment_err_en Enable interrupt for lane alignment error type. Applicable to all lanes. RW 0x1
12 frame_alignment_err_en Enable interrupt for frame alignment error type. Applicable to all lanes. RW 0x1
11 cg_sync_err_en Enable interrupt for code group synchronization error type. Applicable to all lanes. RW 0x1
10 src_rx_alarm_en Enable interrupt for rx_alarm error assertion from Tile SRC RW 0x1
9 syspll_lock_err_en Enable interrupt for system PLL unlock error. RW 0x1
8 rs4_en RX error enable reserve 4 RW 0x1
7 efifo_underflow_err_en Enable interrupt for System clock Elastic FIFO empty error. RW 0x1
6 efifo_overflow_err_en Enable interrupt for System clock Elastic FIFO full error. RW 0x1
5 rx_locked_to_data_err_en Enable interrupt for RX is not locked to data error. RW 0x1
4 lane_deskew_err_en Enable interrupt for lane deskew error type. RW 0x1
3 frame_data_ready_err_en Enable interrupt for transport layer data ready error type. RW 0x1
2 dll_data_ready_err_en Enable interrupt for DLL data ready error type. RW 0x1
1 sysref_lmfc_err_en Enable interrupt for SYSREF LMFC error type. RW 0x1
0 Reserved Reserved RV 0x0
Table 72.  rx_err_link_reinitThis register enables the error types that will generate link reinit. Link reinitialization is entered by the FPGA IP by asserting SYNC_N low. Setting 0 to the register bits will disable the specific error type from link reinitialization. Code group synchronization error does not have an enabled bit because the F-Tile JESD204B specification requires code group error to deassert SYNC_N and request for link reinitialization.

0: Do not reinitialize even if the particular error type is triggered. (Default)

1: Reinitialize if the particular error type is triggered.

Offset: 0x78
Bit Name Description Attribute Reset
31:21 Reserved Reserved RV 0x0
20 ecc_err_fatal_link_reinit Enable link reinitialization for ECC fatal error type. Applicable to all lanes. User is not recommended to reinit since ECC error is not due to link issue. RW 0x0
19 ecc_err_corrected_link_reinit Enable link reinitialization for ECC correctable error type. Applicable to all lanes. User is not recommended to reinit since ECC error is self-recovered. RW 0x0
18 dllerr_rs_link_reinit DLL error 1 link reinit enable reserve. Applicable to all lanes. RW 0x0
17 ilas_err_link_reinit Enable link reinitialization for missing ILAS error type. Applicable to all lanes. RW 0x0
16 disparity_err_link_reinit Enable link reinitialization for disparity error type. Applicable to all lanes. RW 0x0
15 not_in_table_err_link_reinit Enable link reinitialization for not in table error type. Applicable to all lanes. RW 0x0
14 unexpected_kchar_link_reinit Enable link reinitialization for unexpected control character error type. Applicable to all lanes. RW 0x0
13 lane_alignment_err_link_reinit Enable link reinitialization for lane alignment error type. Applicable to all lanes. RW 0x1
12 frame_alignment_err_link_reinit Enable link re-initialization for frame alignment error type. Applicable to all lanes. RW 0x1
11 cg_sync_err_link_reinit Enable link reinitialization for code group synchronization error. ROV 0x1
10 Reserved Reserved RV 0x0
9 Reserved Reserved RV 0x0
8 rs4_link_reinit RX error link reinit enable reserve 4 RW 0x1
7 Reserved Reserved RV 0x0
6 Reserved Reserved RV 0x0
5 rx_locked_to_data_err_link_reinit Enable link reinitialization for RX is not locked to data error. RW 0x0
4 lane_deskew_err_link_reinit Enable link reinitialization for lane deskew error type. RW 0x0
3 frame_data_ready_err_link_reinit Enable link reinitialization for Transport Layer data ready error type. RW 0x0
2 dll_data_ready_err_link_reinit Enable link reinitialization for DLL data ready error type. RW 0x0
1 sysref_lmfc_err_link_reinit Enable link reinitialization for SYSREF LMFC error type. RW 0x1
0 Reserved Reserved RV 0x0
Table 73.  rx_status0Monitor ports of internal signals and counter which will be useful for debug.

Offset: 0x80
Bit Name Description Attribute Reset
31:19 Reserved Reserved RV 0x0
18 rs8 Reserved ROV 0x0
17 rs7 Reserved ROV 0x0
16 rs6 Reserved ROV 0x0
15 rs5 Reserved ROV 0x0
14 rs4 Reserved ROV 0x0
13 rs3 Reserved ROV 0x0
12 rs2 Reserved ROV 0x0
11 rs1 Reserved ROV 0x0
10:3 rbd_count

This is a binary minus 1 value. Legal value reported from this register is ((FxK/4)-1) to 0.

  • When rbd_count = 0, this indicates that the latest lane arrives within the link at the LMFC boundary.
  • When rbd_count = 1, this indicates that the latest lane arrives within the link at 1 link clock cycle before the LMFC boundary.
Note: When the latest lane arrival in the link is too close to the LMFC boundary, Intel recommends to set the RBD release opportunity (sysref_ctrl 0x54 rbd_offset) at least 2 link clocks away from the rbd_count register to accommodate for worst-case power cycle variation.
ROV 0x0
2:1 Reserved Reserved RV 0x0
0 dev_syncn

Internal SYNC_N value.

  • 0 = Receiver is asserting synchronization request.
  • 1 = JESD204B link is out of synchronization

.

 ROV 0x0
Table 74.  rx_status1Monitor ports of internal signals and counter which will be useful for debug.

Offset: 0x84
Bit Name Description Attribute Reset
31 lane7_rx_desired_state SIP Reset Sequencer control for lane7 ROV 0x0
30:28 lane7_rx_current_state[2:0] Tile SRC status for lane7 ROV 0x0
27 lane6_rx_desired_state SIP Reset Sequencer control for lane6 ROV 0x0
26:24 lane6_rx_current_state[2:0] Tile SRC status for lane6 ROV 0x0
23 lane5_rx_desired_state SIP Reset Sequencer control for lane5 ROV 0x0
22:20 lane5_rx_current_state[2:0] Tile SRC status for lane5 ROV 0x0
19 lane4_rx_desired_state SIP Reset Sequencer control for lane4 ROV 0x0
18:16 lane4_rx_current_state[2:0] Tile SRC status for lane4 ROV 0x0
15 lane3_rx_desired_state SIP Reset Sequencer control for lane3 ROV 0x0
14:12 lane3_rx_current_state[2:0] Tile SRC status for lane3 ROV 0x0
11 lane2_rx_desired_state SIP Reset Sequencer control for lane2 ROV 0x0
10:8 lane2_rx_current_state[2:0] Tile SRC status for lane2 ROV 0x0
7 lane1_rx_desired_state SIP Reset Sequencer control for lane1 ROV 0x0
6:4 lane1_rx_current_state[2:0] Tile SRC status for lane1 ROV 0x0
3 lane0_rx_desired_state SIP Reset Sequencer control for lane0 ROV 0x0
2:0 lane0_rx_current_state[2:0] Tile SRC status for lane0 ROV 0x0
Table 75.  rx_status2Monitor ports of internal signals and counter which will be useful for debug.

Offset: 0x88
Bit Name Description Attribute Reset
31:24 Reserved Reserved RV 0x0
23 lane7_pcs_valid PCS status for lane 7, indicates PCS is valid, the correct word boundary has been found and aligned to it. ROV 0x0
22 lane6_pcs_valid PCS status for lane 6, indicates PCS is valid, the correct word boundary has been found and aligned to it. ROV 0x0
21 lane5_pcs_valid PCS status for lane 5, indicates PCS is valid, the correct word boundary has been found and aligned to it. ROV 0x0
20 lane4_pcs_valid PCS status for lane 4, indicates PCS is valid, the correct word boundary has been found and aligned to it. ROV 0x0
19 lane3_pcs_valid PCS status for lane 3, indicates PCS is valid, the correct word boundary has been found and aligned to it. ROV 0x0
18 lane2_pcs_valid PCS status for lane 2, indicates PCS is valid, the correct word boundary has been found and aligned to it. ROV 0x0
17 lane1_pcs_valid PCS status for lane 1, indicates PCS is valid, the correct word boundary has been found and aligned to it. ROV 0x0
16 lane0_pcs_valid PCS status for lane 0, indicates PCS is valid, the correct word boundary has been found and aligned to it. ROV 0x0
15:8 Reserved Reserved RV 0x0
7 rs28 Reserved status 8. ROV 0x0
6 rs27 Reserved status 7. ROV 0x0
5 rs26 Reserved status 6. ROV 0x0
4 rs25 Reserved status 5. ROV 0x0
3 rs24 Reserved status 4. ROV 0x0
2 rs23 Reserved status 3. ROV 0x0
1 rs22 Reserved status 2. ROV 0x0
0 rs21 Reserved status 1. ROV 0x0
Table 76.  rx_status3Monitor ports of internal signals and counter which will be useful for debug.

Offset: 0x8C
Bit Name Description Attribute Reset
31:8 Reserved Reserved RV 0x0
7 lane7_rx_locked_to_data When asserted, indicates that the RX CDR PLL for lane 7 is locked to the RX data and that the RX CDR has changed from LTR to LTD mode. ROV 0x0
6 lane6_rx_locked_to_data When asserted, indicates that the RX CDR PLL for lane 6 is locked to the RX data and that the RX CDR has changed from LTR to LTD mode. ROV 0x0
5 lane5_rx_locked_to_data When asserted, indicates that the RX CDR PLL for lane 5 is locked to the RX data and that the RX CDR has changed from LTR to LTD mode. ROV 0x0
4 lane4_rx_locked_to_data When asserted, indicates that the RX CDR PLL for lane 4 is locked to the RX data and that the RX CDR has changed from LTR to LTD mode. ROV 0x0
3 lane3_rx_locked_to_data When asserted, indicates that the RX CDR PLL for lane 3 is locked to the RX data and that the RX CDR has changed from LTR to LTD mode. ROV 0x0
2 lane2_rx_locked_to_data When asserted, indicates that the RX CDR PLL for lane 2 is locked to the RX data and that the RX CDR has changed from LTR to LTD mode. ROV 0x0
1 lane1_rx_locked_to_data When asserted, indicates that the RX CDR PLL for lane 1 is locked to the RX data and that the RX CDR has changed from LTR to LTD mode. ROV 0x0
0 lane0_rx_locked_to_data When asserted, indicates that the RX CDR PLL for lane 0 is locked to the RX data and that the RX CDR has changed from LTR to LTD mode. ROV 0x0
Table 77.  ilas_data1Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0x94
Bit Name Description Attribute Reset
31:24 M

Link M.

Number of converters per device (binary value minus 1).

 RO Compile-time specific
23:21 Reserved Reserved RV 0x0
20:16 K

Link K.

Number of frames per multiframe (binary value minus 1).

 RO Compile-time specific
15:8 F

Link F.

Number of octets per frame (binary value minus 1).

 RO Compile-time specific
7 scr_en

Enable or disable descrambler.

  • 0 = Disable descrambler
  • 1 = Enable descrambler
 RO Compile-time specific
6:5 Reserved Reserved RV 0x0
4:0 L

Link L.

Number of lanes per converter (binary value minus 1).

 RO Compile-time specific
Table 78.  ilas_data2Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0x98
Bit Name Description Attribute Reset
31 HD

Link HD.

High density format.

 RO Compile-time specific
30:29 Reserved Reserved RV 0x0
28:24 CF

Link CF.

Number of control words per frame clock period per link

  • CF = L is encoded as 31: control words on all lanes.
  • CF = 31 can only occur when L = 31
 RO Compile-time specific
23:21 jesdv

JESD204x version.

  • 000 = JESD204A
  • 001 = JESD204B
 RO Compile-time specific
20:16 S

Link S.

Number of samples per converter per frame cycle (binary value minus 1).

 RO Compile-time specific
15:13 subclassv

Device subclass version

  • 000 = Subclass 0
  • 001 = Subclass 1
  • 010 = Subclass 2
 RO Compile-time specific
12.8 NP

Link NP.

Total number of bits per sample (binary value minus 1).

 RO Compile-time specific
7:6 CS

Link CS.

Number of control bits per sample.

 RO Compile-time specific
5 Reserved Reserved RV 0x0
4:0 N

Link N.

Converter resolution (binary value minus 1).

 RO Compile-time specific
Table 79.  ilas_octet0Link control configuration fields in octets for configuration checking. All of the ILAS configuration data from the converter device is latched and can be accessed through ilas_octet0 (0xA0), ilas_octet1 (0xA4), ilas_octet2 (0xA8), and ilas octet3 (0xAC). To access configuration data transmitted for each individual channel, configure the csr_ilas_data_sel register correctly to multiplex the ILAS configuration data from different channels to these registers.

Offset: 0xA0
Bit Name Description Attribute Reset
31:24 no3 Configuration octet 3: SCR, L ROV 0x00
23:16 no2 Configuration octet 2: ADJDIR, PHADJ, LID ROV 0x00
15:8 no1 Configuration octet 1: ADJCNT, BID ROV 0x00
7:0 no0 Configuration octet 0: DID ROV 0x00
Table 80.  ilas_octet1Link control configuration fields in octets for configuration checking.

Offset: 0xA4
Bit Name Description Attribute Reset
31:24 no7 Configuration octet 7: CS, N ROV 0x00
23:16 no6 Configuration octet 6: M ROV 0x00
15:8 no5 Configuration octet 5: K ROV 0x00
7:0 no4 Configuration octet 4: F ROV 0x00
Table 81.  ilas_octet2Link control configuration fields in octets for configuration checking.

Offset: 0xA8
Bit Name Description Attribute Reset
31:24 no11 Configuration octet 11: RES1 ROV 0x00
23:16 no10 Configuration octet 10: HD, CF ROV 0x00
15:8 no9 Configuration octet 9: JESDV, S ROV 0x00
7:0 no8 Configuration octet 8: SUBCLASSV, N_PRIME ROV 0x00
Table 82.  ilas_octet3Link control configuration fields in octets for configuration checking.

Offset: 0xAC
Bit Name Description Attribute Reset
31:16 Reserved Reserved RV 0x00
15:8 no13 Configuration octet 13: FCHK ROV 0x00
7:0 no12 Configuration octet 12: RES2 ROV 0x00
Table 83.  ilas_data12Link control configuration transmitted during initial lane alignment sequence (ILAS).

Offset: 0xC0
Bit Name Description Attribute Reset
31:10 Reserved Reserved RV 0x0
9:2 fxk_h

Upper bits of FxK[8:2]. This is a binary value minus 1.

Link F multiply with Link K must be divisible by 4.

Note: The IP runs on 32-bit data width boundary per channel, so you must always ensure that FxK must be divisible by 4.
RO Compile-time specific
1:0 fxk_l

Lower bits of FxK[1:0]. This is a binary value minus 1.

Link F multiply with Link K must be divisible by 4.

Note: The IP runs on 32-bit data width boundary per channel, so you must always ensure that FxK must be divisible by 4. FxK (in binary value minus 1) always results to a value of 2'b11 in the lower 2 bits.
RO 0x3
Table 84.  rx_testJESD204 RX test control.

Offset: 0xD0
Bit Name Description Attribute Reset
31:4 Reserved Reserved RV 0x0
3:0 rx_testmode
  • 'b0xxx is reserved for the JESD204B IP
  • 'b1xxx is reserved for external components outside of the JESD204B IP

JESD204B IP test mode.

  • 0000 = No test (Default)
  • 0001 = K28.5
  • 0010 = D21.5

JESD204B IP reference design test Mode:

  • 1000 = Alternating checkerboard
  • 1001 = Ramp
  • 1010 = PRBS
 RW 0x0
Table 85.  rx_status4Monitor ports of internal signals and counter which will be useful for debug.

Offset: 0xF0
Bit Name Description Attribute Reset
31:16 Reserved Reserved ROV 0x0
15:14 lane7_cs_state

Indicates current state of RX DLL code group synchronization state machine for lane 7.

 ROV 0x0
13:12 lane6_cs_state

Indicates current state of RX DLL code group synchronization state machine for lane 6.

 ROV 0x0
11:10 lane5_cs_state

Indicates current state of RX DLL code group synchronization state machine for lane 5.

 ROV 0x0
9:8 lane4_cs_state

Indicates current state of RX DLL code group synchronization state machine for lane 4.

 ROV 0x0
7:6 lane3_cs_state

Indicates current state of RX DLL code group synchronization state machine for lane 3.

 ROV 0x0
5:4 lane2_cs_state

Indicates current state of RX DLL code group synchronization state machine for lane 2.

 ROV 0x0
3:2 lane1_cs_state

Indicates current state of RX DLL code group synchronization state machine for lane 1.

 ROV 0x0
1:0 lane0_cs_state

Indicates current state of RX DLL code group synchronization state machine for lane 0.

 ROV 0x0
Table 86.  rx_status5Monitor ports of internal signals and counter which will be useful for debug.

Offset: 0xF4
Bit Name Description Attribute Reset
31:16 Reserved Reserved RV 0x0
15:14 lane7_fs_state

Indicates current state of RX DLL frame synchronization state machine for lane 7.

 ROV 0x0
13:12 lane6_fs_state

Indicates current state of RX DLL frame synchronization state machine for lane 6.

 ROV 0x0
11:10 lane5_fs_state

Indicates current state of RX DLL frame synchronization state machine for lane 5.

 ROV 0x0
9:8 lane4_fs_state

Indicates current state of RX DLL frame synchronization state machine for lane 4.

 ROV 0x0
7:6 lane3_fs_state

Indicates current state of RX DLL frame synchronization state machine for lane 3.

 ROV 0x0
5:4 lane2_fs_state

Indicates current state of RX DLL frame synchronization state machine for lane 2.

 ROV 0x0
3:2 lane1_fs_state

Indicates current state of RX DLL frame synchronization state machine for lane 1.

 ROV 0x0
1:0 lane0_fs_state

Indicates current state of RX DLL frame synchronization state machine for lane 0.

 ROV 0x0
Table 87.  rx_status6Monitor ports of internal signals and counter which will be useful for debug.

Offset: 0xF8
Bit Name Description Attribute Reset
31:24 Reserved Reserved RV 0x0
23 lane7_rx_fifo_empty Indicates that RX DLL FIFO is empty for lane 7. ROV 0x0
22 lane6_rx_fifo_empty Indicates that RX DLL FIFO is empty for lane 6. ROV 0x0
21 lane5_rx_fifo_empty Indicates that RX DLL FIFO is empty for lane 5. ROV 0x0
20 lane4_rx_fifo_empty Indicates that RX DLL FIFO is empty for lane 4. ROV 0x0
19 lane3_rx_fifo_empty Indicates that RX DLL FIFO is empty for lane 3. ROV 0x0
18 lane2_rx_fifo_empty Indicates that RX DLL FIFO is empty for lane 2. ROV 0x0
17 lane1_rx_fifo_empty Indicates that RX DLL FIFO is empty for lane 1. ROV 0x0
16 lane0_rx_fifo_empty Indicates that RX DLL FIFO is empty for lane 0. ROV 0x0
15:8 Reserved Reserved RV 0x0
7 lane7_rx_fifo_full Indicates that RX DLL lane sync FIFO is full for lane 7. ROV 0x0
6 lane6_rx_fifo_full Indicates that RX DLL lane sync FIFO is full for lane 6. ROV 0x0
5 lane5_rx_fifo_full Indicates that RX DLL lane sync FIFO is full for lane 5. ROV 0x0
4 lane4_rx_fifo_full Indicates that RX DLL lane sync FIFO is full for lane 4. ROV 0x0
3 lane3_rx_fifo_full Indicates that RX DLL lane sync FIFO is full for lane 3. ROV 0x0
2 lane2_rx_fifo_full Indicates that RX DLL lane sync FIFO is full for lane 2. ROV 0x0
1 lane1_rx_fifo_full Indicates that RX DLL lane sync FIFO is full for lane 1. ROV 0x0
0 lane0_rx_fifo_full Indicates that RX DLL lane sync FIFO is full for lane 0. ROV 0x0
Table 88.  rx_status7Monitor ports of internal signals and counter which will be useful for debug.

Offset: 0xFC
Bit Name Description Attribute Reset
31:24 Reserved Reserved RV 0x0
23 lane7_ilas_cfg_data_started ILAS CFG data started for lane 7. ROV 0x0
22 lane6_ilas_cfg_data_started ILAS CFG data started for lane 6. ROV 0x0
21 lane5_ilas_cfg_data_started ILAS CFG data started for lane 5. ROV 0x0
20 lane4_ilas_cfg_data_started4 ILAS CFG data started for lane 4. ROV 0x0
19 lane3_ilas_cfg_data_started ILAS CFG data started for lane 3. ROV 0x0
18 lane2_ilas_cfg_data_started ILAS CFG data started for lane 2. ROV 0x0
17 lane1_ilas_cfg_data_started ILAS CFG data started for lane 1. ROV 0x0
16 lane0_ilas_cfg_data_started ILAS CFG data started for lane 0. ROV 0x0
15:8 Reserved Reserved RV 0x0
7 lane7_dll_user_data_phase DLL user data phase for lane 7. ROV 0x0
6 lane6_dll_user_data_phase DLL user data phase for lane 6. ROV 0x0
5 lane5_dll_user_data_phase DLL user data phase for lane 5. ROV 0x0
4 lane4_dll_user_data_phase DLL user data phase for lane 4. ROV 0x0
3 lane3_dll_user_data_phase DLL user data phase for lane 3. ROV 0x0
2 lane2_dll_user_data_phase DLL user data phase for lane 2. ROV 0x0
1 lane1_dll_user_data_phase DLL user data phase for lane 1. ROV 0x0
0 lane0_dll_user_data_phase DLL user data phase for lane 0. ROV 0x0
Table 89.  rx_unusedUnused.

Offset: 0x3FC
Bit Name Description Attribute Reset
31:0 Reserved Reserved RV 0x0
Level Two Title