F-Tile Ethernet Multirate Intel® FPGA IP User Guide

ID 714307
Date 5/01/2024
Public
Document Table of Contents

2.16.2. Time-of-Day Interface

A separate time-of-day (TOD) interface is available for each port within a reconfiguration group. Every time-of-day port in a reconfiguration group must be driven regardless of the number of active ports being used.

For Basic and Advanced timestamp accuracy modes, all time-of-day data must be synchronized to the same master time-of-day module.

The table describes the interface details for different numbers of ports.
Table 68.  Signals of the Time-of-Day (TOD) InterfaceFor signals description, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.
Maximum Number of Ports Applicable Reconfiguration Groups Signal Name
1

FGT:

25GE-1 Reconfigurable

50GE-1 Reconfigurable

FHT:

50GE-1 Reconfigurable

100GE-1 Reconfigurable

Port 0:

i_p0_ptp_tx_tod[95:0]

i_p0_ptp_tx_tod_valid

i_p0_ptp_rx_tod[95:0]

i_p0_ptp_rx_tod_valid

2

FGT:

100GE-2 Reconfigurable

FHT:

100GE-2 Reconfigurable

200GE-2 Reconfigurable

Port 0:

i_p0_ptp_tx_tod[95:0]

i_p0_ptp_tx_tod_valid

i_p0_ptp_rx_tod[95:0]

i_p0_ptp_rx_tod_valid

Port 1:

i_p1_ptp_tx_tod[95:0]

i_p1_ptp_tx_tod_valid

i_p1_ptp_rx_tod[95:0]

i_p1_ptp_rx_tod_valid

4

FGT:

100GE-4 Reconfigurable

400GE-8 Reconfigurable

200GE-4 Reconfigurable

FHT:

100GE-4 Reconfigurable

400GE-4 Reconfigurable

200GE-4 Reconfigurable

Port 0:

i_p0_ptp_tx_tod[95:0]

i_p0_ptp_tx_tod_valid

i_p0_ptp_rx_tod[95:0]

i_p0_ptp_rx_tod_valid

Port 1:

i_p1_ptp_tx_tod[95:0]

i_p1_ptp_tx_tod_valid

i_p1_ptp_rx_tod[95:0]

i_p1_ptp_rx_tod_valid

Port 2:

i_p2_ptp_tx_tod[95:0]

i_p2_ptp_tx_tod_valid

i_p2_ptp_rx_tod[95:0]

i_p2_ptp_rx_tod_valid

Port 3:

i_p3_ptp_tx_tod[95:0]

i_p3_ptp_tx_tod_valid

i_p3_ptp_rx_tod[95:0]

i_p3_ptp_rx_tod_valid