F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

Download PDF
ID 711009
Date 6/21/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core x
1.1. Features 1.2. Design Considerations 1.3. Device Family Support 1.4. Resource Utilization 1.5. Release Information
2. Interface Overview x
2.1. Clock Signals 2.2. Reset 2.3. Avalon® Memory-Mapped Interface 2.4. Control and Status Interface
4. Designing with the IP Core x
4.1. Generating Dynamic Reconfiguration Design and Configuration Profiles 4.2. Dynamic Reconfiguration QSF Settings 4.3. Dynamic Reconfiguration Rules 4.4. Hardware States and Configuration Profiles 4.5. Nios® -Based Dynamic Reconfiguration Flow 4.6. Using the Tile Assignment Editor 4.7. Visualizing Dynamic Reconfiguration Group Placement 4.8. Assigning IP_COLOCATE Hierarchy 4.9. Example: Dynamic Reconfiguration with Multirate IP Flow 4.10. Example: Dynamic Reconfiguration Programming Sequence 4.11. Determining Profile Numbers
4.2. Dynamic Reconfiguration QSF Settings x
4.2.1. Dynamic Reconfiguration Using QSF-driven Flow
4.5. Nios® -Based Dynamic Reconfiguration Flow x
4.5.1. Selecting the Nios® Data Memory Size
4.6. Using the Tile Assignment Editor x
4.6.1. Creating .qsf Assignments 4.6.2. Generating the IP_Colocate QSF Assignment
5. Block Description x
5.1. Clocks 5.2. Reset 5.3. Stack Clocking for Fracturability
6. Configuration Registers x
6.1. Dynamic Reconfiguration New Trigger 6.2. Dynamic Reconfiguration Next Profile 0 6.3. Dynamic Reconfiguration Next Profile 1 6.4. Dynamic Reconfiguration Next Profile 2 6.5. Dynamic Reconfiguration Next Profile 3 6.6. Dynamic Reconfiguration Next Profile 4 6.7. Dynamic Reconfiguration Next Profile 5 6.8. Dynamic Reconfiguration Next Profile 6 6.9. Dynamic Reconfiguration Next Profile 7 6.10. Dynamic Reconfiguration Next Profile 8 6.11. Dynamic Reconfiguration Next Profile 9 6.12. Dynamic Reconfiguration Next Profile 10 6.13. Dynamic Reconfiguration Next Profile 11 6.14. Dynamic Reconfiguration Next Profile 12 6.15. Dynamic Reconfiguration Next Profile 13 6.16. Dynamic Reconfiguration Next Profile 14 6.17. Dynamic Reconfiguration Next Profile 15 6.18. Dynamic Reconfiguration Next Profile 16 6.19. Dynamic Reconfiguration Next Profile 17 6.20. Dynamic Reconfiguration Next Profile 18 6.21. Dynamic Reconfiguration Next Profile 19 6.22. Dynamic Reconfiguration Avalon MM Timeout 6.23. Dynamic Reconfiguration TX Channel Reconfiguration 6.24. Dynamic Reconfiguration RX Channel Reconfiguration 6.25. Dynamic Reconfiguration TX Channel in Reset Acknowledgment 6.26. Dynamic Reconfiguration TX Channel out of Reset 6.27. Dynamic Reconfiguration TX Channel Reset Control Init Status 6.28. Dynamic Reconfiguration TX Channel Source Alarm 6.29. Dynamic Reconfiguration RX Channel in Reset Acknowledgment 6.30. Dynamic Reconfiguration RX Channel out of Reset 6.31. Dynamic Reconfiguration RX Channel Reset Control Init Status 6.32. Dynamic Reconfiguration RX Channel Source Alarm
1. About the F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP Core
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

8. Document Revision History for F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.06.21 22.2 6.0.0
  • Added support for new design example variants:
    • Ethernet base variants:
      • 100G-4 with RS-FEC and PTP
      • 25G-1 with RS-FEC and PTP
      • 400G-8 with RS-FEC and PTP
    • PMA/FEC Direct PHY base variant: 400G-8 with RS-FEC
  • Added new sections:
    • Using the Tile Assignment Editor
    • Determining Profile Numbers
  • Corrected the access type of the following registers:
    • Dynamic Reconfiguration Next Profile 1
    • Dynamic Reconfiguration Next Profile 2
  • Corrected the bit offset of the following registers:
    • Dynamic Reconfiguration TX Channel Reconfiguration
    • Dynamic Reconfiguration TX Channel Reconfiguration
2022.04.22 22.1 5.0.0
  • Revised Features section.
  • Updated the 400G Ethernet and 50G PMA/FEC Direct PHY design example variants in the Resource Utilization.
  • Added PMA/FEC Direct PHY Multirate IP .qsf assignments in Dynamic Reconfiguration QSF Settings.
  • Added typical dynamic reconfiguration software flow in Nios-Based Dynamic Reconfiguration Flow.
  • Added new topics in the Designing with the IP Core chapter:
    • Dynamic Reconfiguration Using QSF-driven Flow
    • Dynamic Reconfiguration Rules
    • Selecting the Nios Data Memory Size
    • Visualizing Dynamic Reconfiguration Group Placement
    • Assigning IP_COLOCATE Hierarchy
    • Example: Dynamic Reconfiguration with Multirate IP Flow
    • Example: Dynamic Reconfiguration Programming Sequence
  • Globally removed FHT support.
2022.02.03 21.4 4.0.0 Initial release.
Level Two Title