F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

Download PDF
ID 710578
Date 1/13/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Interface Overview 3. Parameters 4. Designing with the IP Core 5. Block Description 6. Configuration Registers 7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives 8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide
1. Introduction x
1.1. IP Core Overview 1.2. Release Information 1.3. Device Family Support 1.4. Device Speed Grade Support 1.5. Related Documentation
2. Interface Overview x
2.1. Clock Signals 2.2. Reset Signals 2.3. TX MII Interface (64b/66b) 2.4. RX MII Interface (64b/66b) 2.5. Status Interface for 64b/66b Line Rate 2.6. TX Interface (8b/10b) 2.7. RX Interface (8b/10b) 2.8. Status Interface for 8b/10b Line Rate 2.9. TX Tunnel Interface 2.10. Using TX Tunnel Interface 2.11. RX Tunnel Interface 2.12. Using RX Tunnel Interface 2.13. Status Interface for Tunnel Line Rate 2.14. Serial Interface 2.15. CPRI PHY Reconfiguration Interface 2.16. Datapath Avalon Memory-Mapped Interface 2.17. PMA Avalon Memory-Mapped Interface
2.1. Clock Signals x
2.1.1. Required Clock Frequencies
3. Parameters x
3.1. Analog Parameters for F-Tile IPs 3.2. Sub Profile Parameters Validation 3.3. Adaptation Parameters
4. Designing with the IP Core x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Specifying the IP Core Parameters and Options 4.3. Generated File Structure 4.4. Dynamic Reconfiguration Settings
4.1. Installing and Licensing Intel® FPGA IP Cores x
4.1.1. Intel® FPGA IP Evaluation Mode
4.2. Specifying the IP Core Parameters and Options x
4.2.1. Reference and System PLL Clock for your IP Design
5. Block Description x
5.1. Latency Measurement 5.2. CDR Clock Output 5.3. RX PMA Adaptation
5.1. Latency Measurement x
5.1.1. Deterministic Latency 5.1.2. Calculation for 64b/66b Datapath
1. Introduction
2. Interface Overview
3. Parameters
4. Designing with the IP Core
5. Block Description
6. Configuration Registers
7. F-Tile CPRI PHY Multirate Intel FPGA IP User Guide Archives
8. Document Revision History for the F-Tile CPRI PHY Multirate Intel® FPGA IP User Guide

5.3. RX PMA Adaptation

The RX PMA Adaptation is preconfigured for each line rate during the IP generation. In auto-adaptation, the PMA performs dynamic adaptation on the RX link. Manual tuning, has no dynamic adaptation; you can tune the RX link using the static equalization taps.
Table 42.  RX PMA AdaptationThe following table lists the most optimal mode for each line rate.
Line Rate (Gbps) RX PMA Adaptation
24.33024 Auto-adaptation
12.16512 Auto-adaptation
10.1376 Auto-adaptation
9.8304

Scrambled: auto-adaptation

Unscrambled: manual tuning.
6.144 Manual tuning
4.9152 Manual tuning
3.072 Manual tuning
2.4576 Manual tuning
1.2288 Manual tuning

For RXEQ VGA Gain, RXEQ High Frequency Boost and RXEQ DFE Data Tap1 registers for manual tuning, refer to the F-Tile PMA/FEC Direct PHY Intel FPGA IP Register Map FGT tab.

Related Information
Level Two Title